diff options
Diffstat (limited to 'src/mainboard/sis/sis761')
| -rw-r--r-- | src/mainboard/sis/sis761/Config.lb | 341 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/Options.lb | 358 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/apc_auto.c | 132 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/cache_as_ram_auto.c | 372 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/chip.h | 29 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/cmos.layout | 119 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/get_bus_conf.c | 148 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/irq_tables.c | 166 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/mainboard.c | 35 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/mptable.c | 161 | ||||
| -rw-r--r-- | src/mainboard/sis/sis761/resourcemap.c | 283 |
11 files changed, 0 insertions, 2144 deletions
diff --git a/src/mainboard/sis/sis761/Config.lb b/src/mainboard/sis/sis761/Config.lb deleted file mode 100644 index 46a847f769..0000000000 --- a/src/mainboard/sis/sis761/Config.lb +++ /dev/null @@ -1,341 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) -## Written by Morgan Tsai <my_tsai@sis.com> for SiS. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end - -## -## Compute the start location and size size of -## The linuxBIOS bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of linuxBIOS will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -#needed by irq_tables and mptable and acpi_tables -object get_bus_conf.o - -if HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o -if USE_DCACHE_RAM - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" - action "perl -e 's/.rodata/.rom.data/g' -pi $@" - action "perl -e 's/.text/.section .rom.text/g' -pi $@" - end - end - -end - -if USE_FAILOVER_IMAGE -else - if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb - end -end - - -## -## Build our 16 bit and 32 bit linuxBIOS entry code -## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end - -mainboardinit cpu/x86/32bit/entry32.inc - -if USE_DCACHE_RAM - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end -end - - -## -## Build our reset vector (This is where linuxBIOS is entered) -## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end - -## -## Include an id string (For safe flashing) -## -mainboardinit southbridge/sis/sis966/id.inc -ldscript /southbridge/sis/sis966/id.lds - -## -## ROMSTRAP table for MCP55 -## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE - mainboardinit southbridge/sis/sis966/romstrap.inc - ldscript /southbridge/sis/sis966/romstrap.lds - end -else - if USE_FALLBACK_IMAGE - mainboardinit southbridge/sis/sis966/romstrap.inc - ldscript /southbridge/sis/sis966/romstrap.lds - end -end - -if USE_DCACHE_RAM - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc -end - -### -### This is the early phase of linuxBIOS startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover_failover.lds - end - end -else - if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM - ldscript /arch/i386/lib/failover.lds - end - end -end - -## -## Setup RAM -## -if USE_DCACHE_RAM - - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end -end - -## -## Include the secondary Configuration files -## -if CONFIG_CHIP_NAME - config chip.h -end - -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_AM2 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/sis/sis966 - device pci 0.0 on end # Northbridge - ################################################# - device pci 1.0 on # AGP bridge - chip drivers/pci/onboard # Integrated VGA - device pci 0.0 on end - register "rom_address" = "0xfff80000" - end - end - ################################################# - ## device pci 1.0 on end # PCIE - device pci 2.0 on # LPC - chip superio/ite/it8716f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - - device pci 2.5 on end # IDE (SiS5513) - device pci 2.6 off end # Modem (SiS7013) - device pci 2.7 off end # Audio (SiS7012) - device pci 3.0 on end # USB (SiS7001,USB1.1) - device pci 3.1 on end # USB (SiS7001,USB1.1) - device pci 3.3 on end # USB (SiS7002,USB2.0) - device pci 4.0 on end # NIC (SiS191) - device pci 5.0 on end # SATA (SiS1183) - device pci 6.0 off end # SB PCIE1 (SiS000A) - device pci 7.0 off end # SB PCIE2 (SiS000A) - device pci 9.0 off end # PCI E 6 - device pci a.0 off end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 off end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # Hda - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - #register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - #register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex diff --git a/src/mainboard/sis/sis761/Options.lb b/src/mainboard/sis/sis761/Options.lb deleted file mode 100644 index a7832bc078..0000000000 --- a/src/mainboard/sis/sis761/Options.lb +++ /dev/null @@ -1,358 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) -## Written by Morgan Tsai <my_tsai@sis.com> for SiS. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CROSS_COMPILE -uses CC -uses HOSTCC -uses OBJCOPY -uses CONFIG_CHIP_NAME -uses CONFIG_CONSOLE_VGA -uses CONFIG_USBDEBUG_DIRECT -uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC -uses K8_HT_FREQ_1G_SUPPORT - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses SERIAL_CPU_INIT - -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID - -uses CONFIG_PCI_64BIT_PREF_MEM - -uses CONFIG_LB_MEM_TOPK - -uses CONFIG_AP_CODE_IN_CAR - -uses MEM_TRAIN_SEQ - -uses WAIT_BEFORE_CPUS_INIT - -uses CONFIG_USE_PRINTK_IN_CAR - -### -### Build options -### - -## -## ROM_SIZE is the size of boot ROM that this board will use. -## -default ROM_SIZE=524288 -#default ROM_SIZE=0x100000 - -## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 - -#FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 -#FAILOVER: 4K -default FAILOVER_SIZE=0x01000 - -#more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=0 - -## ACPI tables will be included -default HAVE_ACPI_TABLES=0 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default LinuxBIOS cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=0 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#default SERIAL_CPU_INIT=0 - -default ENABLE_APIC_EXT_ID=0 -default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=1 - -#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. -#2G -#default HW_MEM_HOLE_SIZEK=0x200000 -#1G -default HW_MEM_HOLE_SIZEK=0x100000 -#512M -#default HW_MEM_HOLE_SIZEK=0x80000 - -#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 - -#Opteron K8 1G HT Support -default K8_HT_FREQ_1G_SUPPORT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -#default CONFIG_USBDEBUG_DIRECT=0 - -#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device -default HT_CHAIN_UNITID_BASE=0 - -#real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x6 - -#make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 - -#only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#allow capable device use that above 4G -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## enable CACHE_AS_RAM specifics -## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="SiS" -default MAINBOARD_VENDOR="SIS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -default ROM_IMAGE_SIZE = 65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 32K heap -## -default HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) - -## -## LinuxBIOS C code runs at this location in RAM -## -default _RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## -default CONFIG_USE_PRINTK_IN_CAR=1 - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/sis/sis761/apc_auto.c b/src/mainboard/sis/sis761/apc_auto.c deleted file mode 100644 index 7e4eddaa5c..0000000000 --- a/src/mainboard/sis/sis761/apc_auto.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __ROMCC__ - -#define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 - -#define SET_NB_CFG_54 1 - -//used by raminit -#define QRANK_DIMM_SUPPORT 1 - -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" - -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" - -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - -#include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" - -#include "lib/delay.c" - -//#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" - -#include "northbridge/amd/amdk8/debug.c" - -#include "southbridge/sis/sis966/sis966_early_ctrl.c" - -#include "northbridge/amd/amdk8/amdk8_f.h" - -#include "cpu/x86/mtrr.h" -#include "cpu/amd/mtrr.h" -#include "cpu/x86/tsc.h" - -#include "northbridge/amd/amdk8/amdk8_f_pci.c" -#include "northbridge/amd/amdk8/raminit_f_dqs.c" - -#include "cpu/amd/dualcore/dualcore.c" - -void hardwaremain(int ret_addr) -{ - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM - - struct node_core_id id; - - id = get_node_core_id_x(); - - //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); - - train_ram(id.nodeid, sysinfo, sysinfox); - - /* - go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp - */ - - __asm__ volatile ( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - :: "a"(ret_addr) - ); - - - -} -struct eregs { - uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi; - uint32_t vector; - uint32_t error_code; - uint32_t eip; - uint32_t cs; - uint32_t eflags; -}; - -void x86_exception(struct eregs *info) -{ - do { - hlt(); - } while(1); -} - - diff --git a/src/mainboard/sis/sis761/cache_as_ram_auto.c b/src/mainboard/sis/sis761/cache_as_ram_auto.c deleted file mode 100644 index 732027adca..0000000000 --- a/src/mainboard/sis/sis761/cache_as_ram_auto.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __ROMCC__ - -#define RAMINIT_SYSINFO 1 - -#define K8_ALLOCATE_IO_RANGE 1 -//#define K8_SCAN_PCI_BUS 1 - - -#define QRANK_DIMM_SUPPORT 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - -//used by init_cpus and fidvid -#define K8_SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 - -#if K8_REV_F_SUPPORT == 1 -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 -#endif - -#define DBGP_DEFAULT 7 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" - -#if USE_FAILOVER_IMAGE==0 -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#if CONFIG_USBDEBUG_DIRECT -#include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c" -#include "pc80/usbdebug_direct_serial.c" -#endif -#include "ram/ramtest.c" - -#include <cpu/amd/model_fxx_rev.h> - -#include "southbridge/sis/sis966/sis966_early_smbus.c" -#include "southbridge/sis/sis966/sis966_enable_rom.c" -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" - -#endif - -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/it8716f_early_serial.c" -#include "superio/ite/it8716f/it8716f_early_init.c" - -#if USE_FAILOVER_IMAGE==0 - -#include "cpu/x86/bist.h" - -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "northbridge/amd/amdk8/debug.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" - -#include "northbridge/amd/amdk8/setup_resource_map.c" - -#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) - -#include "southbridge/sis/sis966/sis966_early_ctrl.c" - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - -#include "northbridge/amd/amdk8/incoherent_ht.c" - -#include "northbridge/amd/amdk8/raminit_f.c" - -#include "sdram/generic_sdram.c" - -#include "resourcemap.c" - -#include "cpu/amd/dualcore/dualcore.c" - -#define SIS966_NUM 1 -#define SIS966_USE_NIC 1 -#define SIS966_USE_AZA 1 - -#define SIS966_PCI_E_X_0 0 - -#define SIS966_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ - -#include "southbridge/sis/sis966/sis966_early_setup_ss.h" -#include "southbridge/sis/sis966/sis966_early_setup_car.c" - -#include "cpu/amd/car/copy_and_run.c" - -#include "cpu/amd/car/post_cache_as_ram.c" - -#include "cpu/amd/model_fxx/init_cpus.c" - -#include "cpu/amd/model_fxx/fidvid.c" - -#endif - -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) - -#include "southbridge/sis/sis966/sis966_enable_rom.c" -#include "northbridge/amd/amdk8/early_ht.c" - - -static void sio_setup(void) -{ - - unsigned value; - uint32_t dword; - uint8_t byte; - - byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); - - dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); -} - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the sis966 */ - sis966_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - -#if USE_FAILOVER_IMAGE==0 - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif - }; - - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); - - int needs_reset = 0; - unsigned bsp_apicid = 0; - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } - - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); - - setup_mb_resource_map(); - - uart_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - -#if CONFIG_USBDEBUG_DIRECT - sis966_enable_usbdebug_direct(DBGP_DEFAULT); - early_usbdebug_direct_init(); -#endif - console_init(); - print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); - - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); - -#if MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -#endif - setup_coherent_ht_domain(); // routing table and start other core0 - - wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); -#endif - - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - -#if K8_SET_FIDVID == 1 - - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); - - } - - enable_fid_change(); - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - - init_fidvid_bsp(bsp_apicid); - - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); - - } -#endif - - needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= sis966_early_setup_x(); - - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - allow_all_aps_stop(bsp_apicid); - - //It's the time to set ctrl in sysinfo now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - sis_init_stage1(); - enable_smbus(); - - memreset_setup(); - - //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID - - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - - sis_init_stage2(); - post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now - -} - - -#endif diff --git a/src/mainboard/sis/sis761/chip.h b/src/mainboard/sis/sis761/chip.h deleted file mode 100644 index 8d6d00cac6..0000000000 --- a/src/mainboard/sis/sis761/chip.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -extern struct chip_operations mainboard_sis_sis761_ops; - -struct mainboard_sis_sis761_config { -// int fixup_scsi; -// int fixup_vga; -}; diff --git a/src/mainboard/sis/sis761/cmos.layout b/src/mainboard/sis/sis761/cmos.layout deleted file mode 100644 index 84a5c52278..0000000000 --- a/src/mainboard/sis/sis761/cmos.layout +++ /dev/null @@ -1,119 +0,0 @@ -## -## This file is part of the LinuxBIOS project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 dual_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/sis/sis761/get_bus_conf.c b/src/mainboard/sis/sis761/get_bus_conf.c deleted file mode 100644 index d8b0c0ab5a..0000000000 --- a/src/mainboard/sis/sis761/get_bus_conf.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <string.h> -#include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 -#include <cpu/amd/dualcore.h> -#endif - -#include <cpu/amd/amdk8_sysconf.h> - - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default - unsigned char bus_isa; - unsigned char bus_sis966[8]; //1 - unsigned apicid_sis966; - - -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 -}; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -}; -unsigned bus_type[256]; - -extern void get_sblk_pci1234(void); - -static unsigned get_bus_conf_done = 0; - -void get_bus_conf(void) -{ - - unsigned apicid_base; - unsigned sbdn; - - device_t dev; - int i, j; - - if(get_bus_conf_done==1) return; //do it only once - - get_bus_conf_done = 1; - - sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - sbdn = sysconf.sbdn; - - for(i=0; i<8; i++) { - bus_sis966[i] = 0; - } - - for(i=0;i<256; i++) { - bus_type[i] = 0; - } - - bus_type[0] = 1; //pci - - bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff; - - bus_type[bus_sis966[0]] = 1; - - /* SIS966 */ - dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x06,0)); - if (dev) { - bus_sis966[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_sis966[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_sis966[2]++; - for(j=bus_sis966[1];j<bus_sis966[2]; j++) bus_type[j] = 1; - } - else { - printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06); - - bus_sis966[1] = 2; - bus_sis966[2] = 3; - } - - for(i=2; i<8;i++) { - dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); - if (dev) { - bus_sis966[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - for(j=bus_sis966[i];j<bus_isa; j++) bus_type[j] = 1; - } - else { - printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_sis966[0], sbdn + 0x0a + i - 2 ); - bus_isa = bus_sis966[i-1]+1; - } - } - - -/*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 - apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; -#endif - apicid_sis966 = apicid_base+0; - -} diff --git a/src/mainboard/sis/sis761/irq_tables.c b/src/mainboard/sis/sis761/irq_tables.c deleted file mode 100644 index c87b9d6954..0000000000 --- a/src/mainboard/sis/sis761/irq_tables.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up - - Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> -#include <arch/pirq_routing.h> - -#include <cpu/amd/amdk8_sysconf.h> - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} -extern unsigned char bus_isa; -extern unsigned char bus_sis966[8]; //1 - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - unsigned sbdn; - - uint8_t sum=0; - int i; - - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - sbdn = sysconf.sbdn; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); - - pirq = (void *)(addr); - v = (uint8_t *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = bus_sis966[0]; - pirq->rtr_devfn = ((sbdn+6)<<3)|0; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x0370; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *) ( &pirq->checksum + 1); - slot_num = 0; - - { - device_t dev; - dev = dev_find_slot(0, PCI_DEVFN(2,0)); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ10 - PINTB = IRQ11 - PINTC = IRQ5 - PINTD = IRQ5 - PINTE = IRQ11 - PINTF = IRQ5 - PINTG = IRQ10 - PINTH = IRQ5 - - */ - int i; - uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63}; - uint8_t irq[8]={0x0A,0X0B,0X05,0X05,0X0B,0X05,0X0A,0X0A}; - - for(i=0;i<8;i++) - pci_write_config8(dev, reg[i], irq[i]); - } - - printk_debug("Setting Onboard SiS Southbridge\n"); -// dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE) -// pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1 -1 - pci_write_config8(dev, 0x3C, 0x0B); - dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1 -2 - pci_write_config8(dev, 0x3C, 0x05); - dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0 - pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(4,0)); // 191 (LAN) - pci_write_config8(dev, 0x3C, 0x05); - dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA) - pci_write_config8(dev, 0x3C, 0x0B); -// dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E -// pci_write_config8(dev, 0x3C, 0x0A); -// dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E -// pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia - pci_write_config8(dev, 0x3C, 0x05); - } - -//pci bridge - write_pirq_info(pirq_info, bus_sis966[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk_info("done.\n"); - - return (unsigned long) pirq_info; - -} diff --git a/src/mainboard/sis/sis761/mainboard.c b/src/mainboard/sis/sis761/mainboard.c deleted file mode 100644 index 9e21efdce8..0000000000 --- a/src/mainboard/sis/sis761/mainboard.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "chip.h" - -#if CONFIG_CHIP_NAME == 1 -struct chip_operations mainboard_sis_sis761_ops = { - CHIP_NAME("SiS SiS761GX/SiS966 Mainboard") -}; -#endif diff --git a/src/mainboard/sis/sis761/mptable.c b/src/mainboard/sis/sis761/mptable.c deleted file mode 100644 index 047a187aaa..0000000000 --- a/src/mainboard/sis/sis761/mptable.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai@sis.com> for SiS. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -#include <cpu/amd/amdk8_sysconf.h> -extern unsigned char bus_isa; -extern unsigned char bus_sis966[8]; //1 - -extern unsigned apicid_sis966; - -extern unsigned bus_type[256]; - -void *smp_write_config_table(void *v) -{ - static const char sig[4] = "PCMP"; - static const char oem[8] = "SIS"; - static const char productid[12] = "SiS761GX"; - struct mp_config_table *mc; - unsigned sbdn; - - int i,j; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - memset(mc, 0, sizeof(*mc)); - - memcpy(mc->mpc_signature, sig, sizeof(sig)); - mc->mpc_length = sizeof(*mc); /* initially just the header */ - mc->mpc_spec = 0x04; - mc->mpc_checksum = 0; /* not yet computed */ - memcpy(mc->mpc_oem, oem, sizeof(oem)); - memcpy(mc->mpc_productid, productid, sizeof(productid)); - mc->mpc_oemptr = 0; - mc->mpc_oemsize = 0; - mc->mpc_entry_count = 0; /* No entries yet... */ - mc->mpc_lapic = LAPIC_ADDR; - mc->mpe_length = 0; - mc->mpe_checksum = 0; - mc->reserved = 0; - - smp_write_processors(mc); - - get_bus_conf(); - sbdn = sysconf.sbdn; - -/*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(j= 0; j < 256 ; j++) { - if(bus_type[j]) - smp_write_bus(mc, j, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - -/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev; - struct resource *res; - uint32_t dword; - - dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, apicid_sis966, 0x11, res->base); - } - - dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0xd0001202; - pci_write_config32(dev, 0x84, dword); - - } - } - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# -*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sis966, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sis966, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sis966, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sis966, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sis966, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sis966, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sis966, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sis966, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sis966, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sis966, 0xf); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+1)<<2)|1, apicid_sis966, 0xa); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+2)<<2)|0, apicid_sis966, 0x16); // 22 - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+2)<<2)|1, apicid_sis966, 0x17); // 23 - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+6)<<2)|1, apicid_sis966, 0x17); // 23 - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+5)<<2)|0, apicid_sis966, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+5)<<2)|1, apicid_sis966, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+5)<<2)|2, apicid_sis966, 0x15); // 21 - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[0], ((sbdn+8)<<2)|0, apicid_sis966, 0x16); // 22 - - for(j=7; j>=2; j--) { - if(!bus_sis966[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[j], (0x00<<2)|i, apicid_sis966, 0x10 + (2+j+i+4-sbdn%4)%4); - } - } - - for(j=0; j<2; j++) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[1], ((0x06+j)<<2)|i, apicid_sis966, 0x10 + (2+i+j)%4); - } - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); - mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); - printk_debug("Wrote the mp table end at: %p - %p\n", - mc, smp_next_mpe_entry(mc)); - return smp_next_mpe_entry(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/sis/sis761/resourcemap.c b/src/mainboard/sis/sis761/resourcemap.c deleted file mode 100644 index 7e23ad9cc9..0000000000 --- a/src/mainboard/sis/sis761/resourcemap.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static void setup_mb_resource_map(void) -{ - static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ -// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, - - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, - - }; - - int max; - max = sizeof(register_values)/sizeof(register_values[0]); - setup_resource_map(register_values, max); -} - |