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-rw-r--r--src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c1
-rw-r--r--src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c1
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c1
15 files changed, 0 insertions, 15 deletions
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c
index 20a89c64d1..e54f2aa2fc 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
index b055c4d276..8088857b28 100644
--- a/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
+++ b/src/mainboard/siemens/fa_ehl/variants/fa_ehl/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg fa_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
index 5cfacb8291..4b80c6696f 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
index 78723c2a19..483a88cb02 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* EXT_WAKE0_1V8# */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
index e7b9bd0e3a..cfab8ed062 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
index 593b2cd1cc..d707b3a014 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
index 5de6973727..f97d1a821f 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
@@ -7,7 +7,6 @@
EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
more logical grouping. */
static const struct pad_config gpio_table[] = {
-
/* Southwest Community */
/* PCIE_WAKE[0:3]_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c
index 7b7dad1129..a800d30ef1 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
index 20a89c64d1..e54f2aa2fc 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c
index 7b7dad1129..a800d30ef1 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
index cb7b273591..66b7f1d2a0 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c
index 7b7dad1129..a800d30ef1 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c
index f5638d5144..a352f7bacb 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
index a4ae8a5d2b..a81f88e771 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
@@ -5,7 +5,6 @@
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
-
/* Community 0 - GpioGroup GPP_B */
PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
index 7b7dad1129..a800d30ef1 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
@@ -6,7 +6,6 @@
#include <soc/romstage.h>
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
-
.dq_map[DDR_CH0] = {
{0xf, 0xf0},
{0xf, 0xf0},