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Diffstat (limited to 'src/mainboard/siemens/mc_apl1/variants/mc_apl5')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
index e85161bfe5..c0a7d53f31 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
@@ -20,7 +20,6 @@
void variant_mainboard_final(void)
{
struct device *dev = NULL;
- uint16_t cmd;
/*
* PIR6 register mapping for PCIe root ports
@@ -50,9 +49,7 @@ void variant_mainboard_final(void)
/* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
if (dev) {
- cmd = pci_read_config16(dev, PCI_COMMAND);
- cmd |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, cmd);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe
* to PCI Bridge. */