aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/sapphire/pureplatinumh61/acpi_tables.c')
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/acpi_tables.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
new file mode 100644
index 0000000000..a790b0bea5
--- /dev/null
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Nicola Corna <nicola@corna.info>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}