diff options
Diffstat (limited to 'src/mainboard/samsung/stumpy/chromeos.c')
| -rw-r--r-- | src/mainboard/samsung/stumpy/chromeos.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 8b6716a441..5f2a062065 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> #define GPIO_SPI_WP 68 #define GPIO_REC_MODE 42 @@ -116,20 +117,16 @@ int get_recovery_mode_switch(void) void init_bootmode_straps(void) { #ifdef __PRE_RAM__ - u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - u32 gp_lvl = inl(gpio_base + GP_LVL); u32 flags = 0; /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (gp_lvl3 & (1 << (GPIO_SPI_WP-64))) + if (get_gpio(GPIO_SPI_WP)) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32)))) + if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ - if (gp_lvl & (1 << GPIO_DEV_MODE)) + if (get_gpio(GPIO_DEV_MODE)) flags |= (1 << FLAG_DEV_MODE); pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); |