6 files changed, 58 insertions, 9 deletions
diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
index cdca002ea3..1654128b03 100644
--- a/src/mainboard/rca/rm4100/Kconfig
+++ b/src/mainboard/rca/rm4100/Kconfig
@@ -9,6 +9,7 @@ config BOARD_RCA_RM4100
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
+	select HAVE_SMI_HANDLER
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/rca/rm4100/Makefile.inc b/src/mainboard/rca/rm4100/Makefile.inc
index 5688262e62..38a5a61fdd 100644
--- a/src/mainboard/rca/rm4100/Makefile.inc
+++ b/src/mainboard/rca/rm4100/Makefile.inc
@@ -1 +1,4 @@
 ROMCCFLAGS=-mcpu=p3 -O
+
+smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
+
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
index 2b04ad7d3a..4dff3bea53 100644
--- a/src/mainboard/rca/rm4100/devicetree.cb
+++ b/src/mainboard/rca/rm4100/devicetree.cb
@@ -1,4 +1,9 @@
 chip northbridge/intel/i82830		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/socket_PGA370	# Mobile Celeron Micro-FCBGA Socket 479
+      device apic 0 on end		# APIC
+    end
+  end
   device pci_domain 0 on		# PCI domain
     device pci 0.0 on end		# Host bridge
     device pci 2.0 on end		# VGA (Intel 82830 CGC)
@@ -19,9 +24,7 @@ chip northbridge/intel/i82830		# Northbridge
       device pci 1d.1 on end		# USB UHCI Controller #2
       device pci 1d.2 on end		# USB UHCI Controller #3
       device pci 1d.7 on end		# USB2 EHCI Controller
-      device pci 1e.0 on		# PCI bridge
-        device pci 08.0 on end		# Intel 82801DB PRO/100 VE Ethernet
-      end
+      device pci 1e.0 on end		# PCI bridge
       device pci 1f.0 on		# ISA/LPC bridge
         chip superio/smsc/smscsuperio	# Super I/O
           device pnp 2e.0 off		# Floppy
@@ -61,10 +64,5 @@ chip northbridge/intel/i82830		# Northbridge
       device pci 1f.6 on end		# AC'97 modem
     end
   end
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_PGA370	# Mobile Celeron Micro-FCBGA Socket 479
-      device apic 0 on end		# APIC
-    end
-  end
 end
 
diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c
index cb907496e1..0324266a8d 100644
--- a/src/mainboard/rca/rm4100/mainboard.c
+++ b/src/mainboard/rca/rm4100/mainboard.c
@@ -21,6 +21,18 @@
 #include <device/device.h>
 #include "chip.h"
 
+static void mainboard_init(device_t dev)
+{
+	// TODO Switch parport LEDs again
+}
+
+static void mainboard_enable(device_t dev)
+{
+	// TODO Switch parport LEDs
+	dev->ops->init = mainboard_init;
+}
+ 
 struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
 	CHIP_NAME("RCA RM4100 Mainboard")
 };
diff --git a/src/mainboard/rca/rm4100/mainboard_smi.c b/src/mainboard/rca/rm4100/mainboard_smi.c
new file mode 100644
index 0000000000..3e242359ee
--- /dev/null
+++ b/src/mainboard/rca/rm4100/mainboard_smi.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+	printk_debug("MAINBOARD IO TRAP HANDLER!\n");
+	return 1;
+}
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index cf7464442d..8b70d9ffc7 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -45,6 +45,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
+#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
 
 /**
  * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
@@ -102,11 +103,12 @@ static void mb_early_setup(void)
 
 static void main(unsigned long bist)
 {
-	if (bist == 0)
+	if (bist == 0) {
 		early_mtrr_init();
 		if (memory_initialized()) {
 			hard_reset();
 		}
+	}
 
 	/* Set southbridge and superio gpios */
 	mb_gpio_init();
@@ -118,6 +120,9 @@ static void main(unsigned long bist)
 	/* Halt if there was a built in self test failure. */
 	report_bist_failure(bist);
 
+	/* disable TCO timers */
+	i82801dx_halt_tco_timer();
+
 	/* Setup mainboard specific registers */
 	mb_early_setup();