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-rw-r--r--src/mainboard/purism/librem_skl/devicetree.cb3
-rw-r--r--src/mainboard/purism/librem_whl/devicetree.cb3
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 23c57120f1..2c73280148 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -37,9 +37,6 @@ chip soc/intel/skylake
register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0081"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Disable DPTF
register "dptf_enable" = "0"
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb
index 497a4cca4d..205033230b 100644
--- a/src/mainboard/purism/librem_whl/devicetree.cb
+++ b/src/mainboard/purism/librem_whl/devicetree.cb
@@ -24,9 +24,6 @@ chip soc/intel/cannonlake
.tdp_pl2_override = 28,
}"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"