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-rw-r--r--src/mainboard/protectli/Kconfig1
-rw-r--r--src/mainboard/protectli/vault_kbl/Kconfig59
-rw-r--r--src/mainboard/protectli/vault_kbl/Kconfig.name2
-rw-r--r--src/mainboard/protectli/vault_kbl/Makefile.inc8
-rw-r--r--src/mainboard/protectli/vault_kbl/acpi/ec.asl0
-rw-r--r--src/mainboard/protectli/vault_kbl/acpi/superio.asl0
-rw-r--r--src/mainboard/protectli/vault_kbl/board_info.txt6
-rw-r--r--src/mainboard/protectli/vault_kbl/bootblock.c17
-rw-r--r--src/mainboard/protectli/vault_kbl/data.vbtbin0 -> 4608 bytes
-rw-r--r--src/mainboard/protectli/vault_kbl/devicetree.cb309
-rw-r--r--src/mainboard/protectli/vault_kbl/dsdt.asl25
-rw-r--r--src/mainboard/protectli/vault_kbl/gma-mainboard.ads16
-rw-r--r--src/mainboard/protectli/vault_kbl/gpio.h180
-rw-r--r--src/mainboard/protectli/vault_kbl/ramstage.c21
-rw-r--r--src/mainboard/protectli/vault_kbl/romstage.c66
15 files changed, 709 insertions, 1 deletions
diff --git a/src/mainboard/protectli/Kconfig b/src/mainboard/protectli/Kconfig
index 3a1b7a48e4..1b4152e119 100644
--- a/src/mainboard/protectli/Kconfig
+++ b/src/mainboard/protectli/Kconfig
@@ -10,7 +10,6 @@ endchoice
source "src/mainboard/protectli/*/Kconfig"
config MAINBOARD_VENDOR
- string "Mainboard Vendor"
default "Protectli"
endif # VENDOR_PROTECTLI
diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig
new file mode 100644
index 0000000000..bfafc0bce2
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/Kconfig
@@ -0,0 +1,59 @@
+if BOARD_PROTECTLI_FW6
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
+ select SOC_INTEL_KABYLAKE
+ select SPI_FLASH_MACRONIX
+ select SUPERIO_ITE_IT8772F
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_DIR
+ string
+ default "protectli/vault_kbl"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "FW6"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config MAX_CPUS
+ int
+ default 4
+
+config VGA_BIOS_ID
+ string
+ default "8086,5916" # 8086,5906 for FW6A
+
+config PXE_ROM_ID
+ string
+ default "8086,150c"
+
+config CBFS_SIZE
+ hex
+ default 0x600000
+
+config ADD_FSP_BINARIES
+ bool
+ default y
+
+config FSP_USE_REPO
+ bool
+ default y
+
+endif
diff --git a/src/mainboard/protectli/vault_kbl/Kconfig.name b/src/mainboard/protectli/vault_kbl/Kconfig.name
new file mode 100644
index 0000000000..51a537ad52
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_PROTECTLI_FW6
+ bool "FW6"
diff --git a/src/mainboard/protectli/vault_kbl/Makefile.inc b/src/mainboard/protectli/vault_kbl/Makefile.inc
new file mode 100644
index 0000000000..d7387486bf
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/Makefile.inc
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This file is part of the coreboot project.
+
+bootblock-y += bootblock.c
+
+ramstage-y += ramstage.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/protectli/vault_kbl/acpi/ec.asl b/src/mainboard/protectli/vault_kbl/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/acpi/ec.asl
diff --git a/src/mainboard/protectli/vault_kbl/acpi/superio.asl b/src/mainboard/protectli/vault_kbl/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/acpi/superio.asl
diff --git a/src/mainboard/protectli/vault_kbl/board_info.txt b/src/mainboard/protectli/vault_kbl/board_info.txt
new file mode 100644
index 0000000000..70bd1746e2
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Protectli
+Board name: FW6A/FW6B/FW6C
+Category: sbc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/protectli/vault_kbl/bootblock.c b/src/mainboard/protectli/vault_kbl/bootblock.c
new file mode 100644
index 0000000000..125f9bfa5e
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/bootblock.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <bootblock_common.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include <superio/ite/common/ite.h>
+
+#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
+#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+ ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
+ ite_enable_3vsbsw(GPIO_DEV);
+ ite_kill_watchdog(GPIO_DEV);
+ ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/protectli/vault_kbl/data.vbt b/src/mainboard/protectli/vault_kbl/data.vbt
new file mode 100644
index 0000000000..4379ed1a6e
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/data.vbt
Binary files differ
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
new file mode 100644
index 0000000000..d53e43eba3
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -0,0 +1,309 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
+ register "s0ix_enable" = "1"
+
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x00fc0201"
+ register "gen2_dec" = "0x007c0a01"
+ register "gen3_dec" = "0x000c03e1"
+ register "gen4_dec" = "0x001c02e1"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+ register "eist_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # Enable VT-d
+ register "ignore_vtd" = "0"
+
+ # Enable SERIRQ continuous
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "tcc_offset" = "5" # TCC of 95C
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPwrOptEnable" = "1"
+ register "EnableAzalia" = "0"
+ register "DspEnable" = "0"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "0"
+ register "HeciEnabled" = "1"
+ register "PmTimerDisabled" = "1"
+ register "SaGv" = "SaGv_Enabled"
+ register "SaImguEnable" = "0"
+ register "IslVrCmd" = "2"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "4" # 4s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
+ #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
+ #+----------------+-------+-------+-------+-------+
+ #Note: IccMax settings are moved to SoC code
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ }"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Enable SATA ports 1,2
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "0"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "0"
+
+ # Enable Root ports. 1-6 for LAN and Root Port 9
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[1]" = "1"
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpEnable[8]" = "1" # mPCIe WiFi
+
+ # Enable Advanced Error Reporting for RP 1-6, 9
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ register "PcieRpAdvancedErrorReporting[1]" = "1"
+ register "PcieRpAdvancedErrorReporting[2]" = "1"
+ register "PcieRpAdvancedErrorReporting[3]" = "1"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+
+ # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9
+ register "PcieRpLtrEnable[0]" = "1"
+ register "PcieRpLtrEnable[1]" = "1"
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+ register "PcieRpLtrEnable[5]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+
+ # Enable RP 9 CLKREQ# support
+ register "PcieRpClkReqSupport[8]" = "1"
+ # RP 9 uses CLKREQ0#
+ register "PcieRpClkReqNumber[8]" = "0"
+
+ # Clocks 0-5 for RP 1-6
+ register "PcieRpClkSrcNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[1]" = "1"
+ register "PcieRpClkSrcNumber[2]" = "2"
+ register "PcieRpClkSrcNumber[3]" = "3"
+ register "PcieRpClkSrcNumber[4]" = "4"
+ register "PcieRpClkSrcNumber[5]" = "5"
+ # RP 9 shares CLKSRC5# with RP 6
+ register "PcieRpClkSrcNumber[8]" = "5"
+
+
+ # USB 2.0 enable ports 1-8, disable ports 9-12
+ register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port
+ register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled
+ register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled
+ register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled
+ register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled
+
+ # USB 3.0 enable ports 1-4, disable ports 5-6
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
+
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
+ }"
+
+ # Lock Down CHIPSET_LOCKDOWN_COREBOOT
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 08.0 off end # Gaussian Mixture Model
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 off end # Thermal Subsystem
+ device pci 14.3 off end # Camera I/O Host Controller
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 on end # PCI Express Port 2
+ device pci 1c.2 on end # PCI Express Port 3
+ device pci 1c.3 on end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.5 on end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on # PCI Express Port 9 - WiFi
+ smbios_slot_desc
+ "SlotTypePciExpressMini52pinWithoutBSKO"
+ "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
+ end
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on
+ chip superio/ite/it8772f
+ register "peci_tmpin" = "3"
+ register "tmpin1_mode" = "THERMAL_RESISTOR"
+ register "tmpin2_mode" = "THERMAL_RESISTOR"
+ # FAN2 available on fan header but unused
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 on # Serial Port 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0xa40
+ io 0x62 = 0xa30
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.a off end # IR
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 off end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 off end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl
new file mode 100644
index 0000000000..624806ca04
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/dsdt.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+ #include <soc/intel/skylake/acpi/platform.asl>
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/protectli/vault_kbl/gma-mainboard.ads b/src/mainboard/protectli/vault_kbl/gma-mainboard.ads
new file mode 100644
index 0000000000..b7cae7837a
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+-- This file is part of the coreboot project.
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/protectli/vault_kbl/gpio.h b/src/mainboard/protectli/vault_kbl/gpio.h
new file mode 100644
index 0000000000..3397d79882
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/gpio.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#ifndef _GPIOFW6B_H
+#define _GPIOFW6B_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP),
+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
+/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
+/* PME# */ PAD_CFG_NF(GPP_A11, 20K_PU, DEEP, NF1),
+/* ISH_GP6 */ PAD_NC(GPP_A12, NONE),
+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
+/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE),
+/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
+/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
+/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
+/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
+/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
+/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
+/* CORE_VID0 */ PAD_NC(GPP_B0, NONE),
+/* CORE_VID1 */ PAD_NC(GPP_B1, NONE),
+/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+/* CPU_GP2 */ PAD_NC(GPP_B3, NONE),
+/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
+/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE),
+/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE),
+/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE),
+/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE),
+/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE),
+/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1),
+/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE),
+/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
+/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
+/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
+/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE),
+/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE),
+/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE),
+/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
+/* SM1ALERT# */ PAD_NC(GPP_B23, NONE),
+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
+/* SML0_CLK */ PAD_NC(GPP_C3, NONE),
+/* SML0DATA */ PAD_NC(GPP_C4, NONE),
+/* SML0ALERT# */ PAD_NC(GPP_C5, NONE),
+/* UART0_RXD */ PAD_NC(GPP_C8, NONE),
+/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
+/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE),
+/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE),
+/* UART1_RXD */ PAD_NC(GPP_C12, NONE),
+/* UART1_TXD */ PAD_NC(GPP_C13, NONE),
+/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE),
+/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE),
+/* I2C0_SDA */ PAD_NC(GPP_C16, NONE),
+/* I2C0_SCL */ PAD_NC(GPP_C17, NONE),
+/* I2C1_SDA */ PAD_NC(GPP_C18, NONE),
+/* I2C1_SCL */ PAD_NC(GPP_C19, NONE),
+/* UART2_RXD */ PAD_NC(GPP_C20, NONE),
+/* UART2_TXD */ PAD_NC(GPP_C21, NONE),
+/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE),
+/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE),
+/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE),
+/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE),
+/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE),
+/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE),
+/* FLASHTRIG */ PAD_NC(GPP_D4, NONE),
+/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
+/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
+/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
+/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
+/* GPP_D9 */ PAD_NC(GPP_D9, NONE),
+/* GPP_D10 */ PAD_NC(GPP_D10, NONE),
+/* GPP_D11 */ PAD_NC(GPP_D11, NONE),
+/* GPP_D12 */ PAD_NC(GPP_D12, NONE),
+/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
+/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
+/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE),
+/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE),
+/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE),
+/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE),
+/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE),
+/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE),
+/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE),
+/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE),
+/* I2S_MCLK */ PAD_NC(GPP_D23, NONE),
+/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE),
+/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE),
+/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE),
+/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),
+/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
+/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),
+/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),
+/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),
+/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE),
+/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE),
+/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE),
+/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE),
+/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDI2_HPD */ PAD_NC(GPP_E14, NONE),
+/* DDI3_HPD */ PAD_NC(GPP_E15, NONE),
+/* DDI4_HPD */ PAD_NC(GPP_E16, NONE),
+/* EDP_HPD */ PAD_NC(GPP_E17, NONE),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
+/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
+/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
+/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
+/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE),
+/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE),
+/* I2S2_TXD */ PAD_NC(GPP_F2, NONE),
+/* I2S2_RXD */ PAD_NC(GPP_F3, NONE),
+/* I2C2_SDA */ PAD_NC(GPP_F4, NONE),
+/* I2C2_SCL */ PAD_NC(GPP_F5, NONE),
+/* I2C3_SDA */ PAD_NC(GPP_F6, NONE),
+/* I2C3_SCL */ PAD_NC(GPP_F7, NONE),
+/* I2C4_SDA */ PAD_NC(GPP_F8, NONE),
+/* I2C4_SDA */ PAD_NC(GPP_F9, NONE),
+/* I2C5_SDA */ PAD_NC(GPP_F10, NONE),
+/* I2C5_SCL */ PAD_NC(GPP_F11, NONE),
+/* EMMC_CMD */ PAD_NC(GPP_F12, NONE),
+/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE),
+/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE),
+/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE),
+/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE),
+/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE),
+/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE),
+/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE),
+/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE),
+/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE),
+/* EMMC_CLK */ PAD_NC(GPP_F22, NONE),
+/* GPP_F23 */ PAD_NC(GPP_F23, NONE),
+/* SD_CMD */ PAD_NC(GPP_G0, NONE),
+/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
+/* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
+/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
+/* SD_DATA3 */ PAD_NC(GPP_G4, NONE),
+/* SD_CD# */ PAD_NC(GPP_G5, NONE),
+/* SD_CLK */ PAD_NC(GPP_G6, NONE),
+/* SD_WP */ PAD_NC(GPP_G7, NONE),
+/* PCH_BATLOW */ PAD_NC(GPD0, NONE),
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* LAN_WAKE_N */ PAD_NC(GPD2, NONE),
+/* PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP),
+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE),
+/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+/* LANPHYC */ PAD_NC(GPD11, NONE),
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c
new file mode 100644
index 0000000000..e9273ba907
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/ramstage.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <bootstate.h>
+#include <soc/ramstage.h>
+
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /*
+ * Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization.
+ */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+ params->TurboMode = 1;
+ params->PchThermalDeviceEnable = 0;
+ params->PchPort61hEnable = 1;
+ params->CdClock = 3;
+}
diff --git a/src/mainboard/protectli/vault_kbl/romstage.c b/src/mainboard/protectli/vault_kbl/romstage.c
new file mode 100644
index 0000000000..e65151bc0e
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/romstage.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
+{
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
+ memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
+}
+
+static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
+{
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 2, 3, 4, 5, 6, 7 },
+ { 1, 0, 2, 3, 4, 5, 6, 7 } };
+ memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
+ memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
+}
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
+ &mem_cfg->DqByteMapCh1);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
+ &mem_cfg->DqsMapCpu2DramCh1);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52, },
+ };
+
+ mem_cfg->DqPinsInterleaved = 1;
+ mem_cfg->CaVrefConfig = 2;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 07:05:54 +0000