diff options
Diffstat (limited to 'src/mainboard/protectli')
| -rw-r--r-- | src/mainboard/protectli/vault_cml/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/protectli/vault_ehl/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 14e604890e..01c5df7724 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" register "cpu_pl2_4_cfg" = "baseline" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index bfb7937c71..df0dbdfdb0 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -8,7 +8,7 @@ chip soc/intel/elkhartlake }" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable lpss s0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3369502b0b..9b0357f654 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "eist_enable" = "1" + register "eist_enable" = "true" # Disable DPTF register "dptf_enable" = "0" |