diff options
Diffstat (limited to 'src/mainboard/prodrive')
| -rw-r--r-- | src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 532ab9f3c8..b3649f906e 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -54,13 +54,13 @@ chip soc/intel/cannonlake register "PcieRpEnable[15]" = "1" # M2 Slot E x1 register "PcieRpEnable[20]" = "1" # Slot 1 x4 # Set MaxPayload to 256 bytes - register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[20]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[20]" = "1" - # Disable Aspm - register "PcieRpAspm[20]" = "AspmDisabled" + register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[20]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[20]" = "1" + # Disable Aspm + register "PcieRpAspm[20]" = "AspmDisabled" # Controls the CLKREQ, not the output directly. # Depends on the CLKREQ to CLK gen mapping below |