diff options
Diffstat (limited to 'src/mainboard/prodrive/atlas/gpio.c')
| -rw-r--r-- | src/mainboard/prodrive/atlas/gpio.c | 55 |
1 files changed, 41 insertions, 14 deletions
diff --git a/src/mainboard/prodrive/atlas/gpio.c b/src/mainboard/prodrive/atlas/gpio.c index fd75900f73..bccb85a739 100644 --- a/src/mainboard/prodrive/atlas/gpio.c +++ b/src/mainboard/prodrive/atlas/gpio.c @@ -4,7 +4,35 @@ #include "gpio.h" -/* Pad configuration in ramstage */ +/* + * Pad configuration in ramstage + * Intel Client PCIe* controller expects each device should drive the SRCCLKREQ#. + * If the GPIO is set to native mode for a device, which do not support SRCCLKREQ#, + * then during RTD3 exit link would not be established. Because controller samples + * the SRCCLKREQ# before detecting the device and break L1 as the system might enter L1SS + * as controller detects SRCCLKREQ# as de-asserted. + * As a workaround the Pins must not be configured in Native Mode (CLKREQ mode). + * Therefore here they are not configured at all. + * source: 689882 (intel document ID) + * + * So apparently hardware doesn't sample SRCCLKREQ Pin if it's not configured as such. + * That workaround suggestion however also brought a patch to FSP, which in + * turn causes the same Bug (even if SRCLKREQ are not configured). Usually + * in order to make use of root port power saving features (e.g. + * clock gating), the Root port must either be disabled or a CLKREQ Pin + * must be configured. The patch however removed that check before + * enabling power management for the rootport. + * Workaround (until FSP is fixed): + * + * Workaround: + * pretend to FSP that the rootports have a CLKREQ Pin attached, by supplying them in the + * FSP UPDs. That will cause FSP to configure the Pin or CLKREQ and enable power + * management for said rootport, but it will not crash on L1 entry/exit. That has been done + * on the Atlas board (as workaround) for a short period of time (before applying FSP Fix) + * like this: + * - memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // RP 5 (the rootport you want to fix) + * - memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; // e.g. choose a clkreq pin that is not routed out + */ static const struct pad_config gpio_table[] = { /* * Do not program virtual wire CPU CLKREQ pins, since CLKREQ of cpu rootports are not @@ -13,7 +41,8 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ PAD_NC(GPP_A7, NONE), - PAD_NC(GPP_A12, NONE), + PAD_CFG_GPI(GPP_A8, NONE, DEEP), // HSID_0 / CLKREQ 7 + //PAD_NC(GPP_A12, NONE), CLKREQ 9B ??? PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // USB_2_3_OC_N PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // USB_4_5_OC_N PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_6_7_OC_N @@ -46,15 +75,10 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D1, NONE), PAD_NC(GPP_D2, NONE), PAD_NC(GPP_D3, NONE), - PAD_NC(GPP_D5, NONE), - /* - * If this pin is configured by coreboot the pci device (i225) connected to this pin - * will not show up in lspci tool in anymore. Configuring CLKREQ seems to be an issue - * with current FSP-S. see also comment at top of file. - */ - //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // PHY0_CLKREQ - PAD_NC(GPP_D7, NONE), - PAD_NC(GPP_D8, NONE), + //PAD_NC(GPP_D5, NONE), CLKREQ 0 + //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // PHY0_CLKREQ / CLKREQ 1 + //PAD_NC(GPP_D7, NONE), CLKREQ 2 + //PAD_NC(GPP_D8, NONE), CLKREQ 3 PAD_NC(GPP_D9, NONE), PAD_NC(GPP_D10, NONE), PAD_NC(GPP_D11, NONE), @@ -66,7 +90,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D19, NONE), /* ------- GPIO Group GPP_E ------- */ - PAD_NC(GPP_E0, NONE), + //PAD_NC(GPP_E0, NONE), CLKREQ 9 PAD_NC(GPP_E1, NONE), PAD_NC(GPP_E2, NONE), PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* TPM INT (todo: check) */ @@ -74,7 +98,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E5, NONE), PAD_CFG_GPI(GPP_E6, NONE, DEEP), PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE), /* EC SMI# */ - PAD_CFG_GPO(GPP_E8, 1, DEEP), /* PERST_CB_RESET_N */ + PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* PERST_CB_RESET_N */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_0_1_OC_N */ PAD_NC(GPP_E10, NONE), PAD_NC(GPP_E11, NONE), @@ -82,7 +106,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E13, NONE), PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP0_HPD (VGA_RED) */ PAD_NC(GPP_E15, NONE), - PAD_NC(GPP_E16, NONE), + //PAD_NC(GPP_E16, NONE), CLKREQ 8 PAD_NC(GPP_E17, NONE), PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DP3_DDC_CTRLCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DP3_DDC_CTRLDATA */ @@ -103,6 +127,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_F13, NONE, DEEP), PAD_NC(GPP_F17, NONE), PAD_NC(GPP_F18, NONE), + PAD_CFG_GPI(GPP_F19, NONE, DEEP), // HSID_1 / CLKREQ 6 PAD_NC(GPP_F20, NONE), PAD_NC(GPP_F21, NONE), PAD_CFG_GPO(GPP_F22, 1, DEEP), /* PERST_PHY0_N */ @@ -116,6 +141,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H13, NONE), PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), // HSID_3 / CLKREQ 4 + PAD_CFG_GPI(GPP_H23, NONE, DEEP), // HSID_2 / CLKREQ 5 /* ------- GPIO Group GPP_R ------- */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BCLK |