5 files changed, 109 insertions, 8 deletions

diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 432963ed0e..f9a87dd6dd 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -14,7 +14,8 @@
 # GNU General Public License for more details.
 #
 
-if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5
+if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
+	BOARD_PCENGINES_APU5
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -41,6 +42,7 @@ config VARIANT_DIR
 	string
 	default "apu2" if BOARD_PCENGINES_APU2
 	default "apu3" if BOARD_PCENGINES_APU3
+	default "apu4" if BOARD_PCENGINES_APU4
 	default "apu5" if BOARD_PCENGINES_APU5
 
 config DEVICETREE
@@ -51,6 +53,7 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "apu2" if BOARD_PCENGINES_APU2
 	default "apu3" if BOARD_PCENGINES_APU3
+	default "apu4" if BOARD_PCENGINES_APU4
 	default "apu5" if BOARD_PCENGINES_APU5
 
 config MAX_CPUS
@@ -76,7 +79,7 @@ config AGESA_BINARY_PI_FILE
 choice
 	prompt "J19 pins 1-10"
 	default APU2_PINMUX_OFF_C if BOARD_PCENGINES_APU2 || \
-		BOARD_PCENGINES_APU3
+		BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4
 	default APU2_PINMUX_UART_C if BOARD_PCENGINES_APU5
 
 config APU2_PINMUX_OFF_C
@@ -84,7 +87,8 @@ config APU2_PINMUX_OFF_C
 
 config APU2_PINMUX_GPIO0
 	bool "GPIO"
-	depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3
+	depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
+		BOARD_PCENGINES_APU4
 
 config APU2_PINMUX_UART_C
 	bool "UART 0x3e8"
@@ -94,7 +98,7 @@ endchoice
 choice
 	prompt "J19 pins 11-20"
 	default APU2_PINMUX_OFF_D if BOARD_PCENGINES_APU2 || \
-		BOARD_PCENGINES_APU3
+		BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4
 	default APU2_PINMUX_UART_D if BOARD_PCENGINES_APU5
 
 config APU2_PINMUX_OFF_D
@@ -102,7 +106,8 @@ config APU2_PINMUX_OFF_D
 
 config APU2_PINMUX_GPIO1
 	bool "GPIO"
-	depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3
+	depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
+		BOARD_PCENGINES_APU4
 
 config APU2_PINMUX_UART_D
 	bool "UART 0x2e8"
diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name
index 68e6d6e8c3..45ec16fde8 100644
--- a/src/mainboard/pcengines/apu2/Kconfig.name
+++ b/src/mainboard/pcengines/apu2/Kconfig.name
@@ -4,5 +4,8 @@ config BOARD_PCENGINES_APU2
 config BOARD_PCENGINES_APU3
 	bool "APU3"
 
+config BOARD_PCENGINES_APU4
+	bool "APU4"
+
 config BOARD_PCENGINES_APU5
 	bool "APU5"
diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt
index f7d5172d16..ec2cc9d071 100644
--- a/src/mainboard/pcengines/apu2/board_info.txt
+++ b/src/mainboard/pcengines/apu2/board_info.txt
@@ -1,4 +1,4 @@
-Board name: apu2 apu3 apu5
+Board name: apu2 apu3 apu4 apu5
 Board URL: http://www.pcengines.ch/apu2c2.htm
 Category: half
 ROM package: SOIC-8
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 14335185b8..6339d94abf 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -117,7 +117,8 @@ static void early_lpc_init(void)
 	// Configure output disabled, value low, pull up/down disabled
 	//
 	if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) ||
-		IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) {
+		IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
+		IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
 		configure_gpio(ACPI_MMIO_BASE,
 			IOMUX_GPIO_32, Function0, GPIO_32, setting);
 	}
@@ -129,7 +130,8 @@ static void early_lpc_init(void)
 	// Configure output enabled, value low, pull up/down disabled
 	//
 	setting = 0x1 << GPIO_OUTPUT_ENABLE;
-	if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) {
+	if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
+		IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
 		configure_gpio(ACPI_MMIO_BASE,
 			IOMUX_GPIO_33, Function0, GPIO_33, setting);
 	}
diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
new file mode 100644
index 0000000000..9859255fad
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
@@ -0,0 +1,91 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/pi/00730F01/root_complex
+	device cpu_cluster 0 on
+		chip cpu/amd/pi/00730F01
+			device lapic 0 on  end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1022 0x1410 inherit
+		chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+
+			chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
+				device pci 0.0 on  end # Root Complex
+				device pci 0.2 off end # IOMMU
+				device pci 1.0 off  end # Internal Graphics P2P bridge 0x9804
+				device pci 1.1 off  end # Internal Multimedia
+				device pci 2.0 on  end # PCIe Host Bridge
+				device pci 2.1 on  end # LAN1
+				device pci 2.2 on  end # LAN2
+				device pci 2.3 on  end # LAN3
+				device pci 2.4 on  end # LAN4
+				device pci 2.5 on  end # mPCIe slot 1
+				device pci 8.0 on  end # Platform Security Processor
+			end	#chip northbridge/amd/pi/00730F01
+
+			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
+				device pci 10.0 on  end # XHCI HC0 muxed with EHCI 2
+				device pci 11.0 on  end # SATA
+				device pci 12.0 on  end # USB EHCI0 usb[0:3] is connected
+				device pci 13.0 on  end # USB EHCI1 usb[4:7]
+				device pci 14.0 on  end # SM
+				device pci 14.3 on      # LPC 0x439d
+					chip superio/nuvoton/nct5104d # SIO NCT5104D
+						register "irq_trigger_type" = "0"
+						device pnp 2e.0 off end
+						device pnp 2e.2 on
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.10 on
+							# UART C is conditionally turned on
+							io 0x60 = 0x3e8
+							irq 0x70 = 4
+						end
+						device pnp 2e.11 on
+							# UART D is conditionally turned on
+							io 0x60 = 0x2e8
+							irq 0x70 = 3
+						end
+						device pnp 2e.8 off end
+						device pnp 2e.f off end
+						# GPIO0 and GPIO1 are conditionally turned on
+						device pnp 2e.007 on end
+						device pnp 2e.107 on end
+						device pnp 2e.607 off end
+						device pnp 2e.e off end
+					end # SIO NCT5104D
+				end # LPC 0x439d
+
+				device pci 14.7 on  end # SD
+				device pci 16.0 on  end # USB EHCI2 usb[8:7] - muxed with XHCI
+			end	#chip southbridge/amd/pi/hudson
+
+			device pci 18.0 on  end
+			device pci 18.1 on  end
+			device pci 18.2 on  end
+			device pci 18.3 on  end
+			device pci 18.4 on  end
+			device pci 18.5 on  end
+
+		end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
+	end #domain
+end #northbridge/amd/pi/00730F01/root_complex