aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/pcengines
diff options
context:
space:
mode:
Diffstat (limited to 'src/mainboard/pcengines')
-rw-r--r--src/mainboard/pcengines/apu1/romstage.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index cf4f3fa370..f8e6318773 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -51,9 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
- __writemsr (0xc0010062, 0);
-
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {