diff options
Diffstat (limited to 'src/mainboard/pcengines/apu2')
-rw-r--r-- | src/mainboard/pcengines/apu2/BiosCallOuts.c | 14 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/Kconfig | 26 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/Kconfig.name | 6 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/Makefile.inc | 2 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/board_info.txt | 2 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/gpio_ftns.h | 25 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 19 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb (renamed from src/mainboard/pcengines/apu2/devicetree.cb) | 0 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 94 | ||||
-rw-r--r-- | src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb | 93 |
10 files changed, 262 insertions, 19 deletions
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 071de97e99..8e2636bdfc 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -90,8 +90,18 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) /* EHCI configuration */ FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + + if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2)) { + // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = FALSE; + } else { + // Enable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = TRUE; + } + + // Enable EHCI 1 ( port 4 to 7) + // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + FchParams->Usb.Ehci2Enable = TRUE; /* sata configuration */ FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index cbcbb7cd63..432963ed0e 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -14,7 +14,7 @@ # GNU General Public License for more details. # -if BOARD_PCENGINES_APU2 +if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -37,9 +37,21 @@ config MAINBOARD_DIR string default pcengines/apu2 +config VARIANT_DIR + string + default "apu2" if BOARD_PCENGINES_APU2 + default "apu3" if BOARD_PCENGINES_APU3 + default "apu5" if BOARD_PCENGINES_APU5 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_PART_NUMBER string - default "apu2" + default "apu2" if BOARD_PCENGINES_APU2 + default "apu3" if BOARD_PCENGINES_APU3 + default "apu5" if BOARD_PCENGINES_APU5 config MAX_CPUS int @@ -63,13 +75,16 @@ config AGESA_BINARY_PI_FILE choice prompt "J19 pins 1-10" - default APU2_PINMUX_OFF_C + default APU2_PINMUX_OFF_C if BOARD_PCENGINES_APU2 || \ + BOARD_PCENGINES_APU3 + default APU2_PINMUX_UART_C if BOARD_PCENGINES_APU5 config APU2_PINMUX_OFF_C bool "disable" config APU2_PINMUX_GPIO0 bool "GPIO" + depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 config APU2_PINMUX_UART_C bool "UART 0x3e8" @@ -78,13 +93,16 @@ endchoice choice prompt "J19 pins 11-20" - default APU2_PINMUX_OFF_D + default APU2_PINMUX_OFF_D if BOARD_PCENGINES_APU2 || \ + BOARD_PCENGINES_APU3 + default APU2_PINMUX_UART_D if BOARD_PCENGINES_APU5 config APU2_PINMUX_OFF_D bool "disable" config APU2_PINMUX_GPIO1 bool "GPIO" + depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 config APU2_PINMUX_UART_D bool "UART 0x2e8" diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name index ab19ee4d8a..68e6d6e8c3 100644 --- a/src/mainboard/pcengines/apu2/Kconfig.name +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -1,2 +1,8 @@ config BOARD_PCENGINES_APU2 bool "APU2" + +config BOARD_PCENGINES_APU3 + bool "APU3" + +config BOARD_PCENGINES_APU5 + bool "APU5" diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 3724b1748e..0e897400ec 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -24,3 +24,5 @@ ramstage-y += gpio_ftns.c # Order of names in SPD_SOURCES is important! SPD_SOURCES = HYNIX-2G-1333 SPD_SOURCES += HYNIX-4G-1333-ECC + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt index 506d43fabe..f7d5172d16 100644 --- a/src/mainboard/pcengines/apu2/board_info.txt +++ b/src/mainboard/pcengines/apu2/board_info.txt @@ -1,4 +1,4 @@ -Board name: apu2 +Board name: apu2 apu3 apu5 Board URL: http://www.pcengines.ch/apu2c2.htm Category: half ROM package: SOIC-8 diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 181349609d..e08ee7bcac 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -23,33 +23,36 @@ int get_spd_offset(void); #define GPIO_OFFSET 0x1500 // -// Based on PC Engines APU2C schematics +// Based on PC Engines APU2C and APU3A schematics // http://www.pcengines.ch/schema/apu2c.pdf +// http://www.pcengines.ch/schema/apu3a.pdf // -#define IOMUX_GPIO_32 0x59 // MODESW +#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) +#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) #define IOMUX_GPIO_49 0x40 // STRAP0 #define IOMUX_GPIO_50 0x41 // STRAP1 -#define IOMUX_GPIO_51 0x42 // PE3 Reset -#define IOMUX_GPIO_55 0x43 // PE4 Reset +#define IOMUX_GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5) +#define IOMUX_GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5) #define IOMUX_GPIO_57 0x44 // LED1# #define IOMUX_GPIO_58 0x45 // LED2# #define IOMUX_GPIO_59 0x46 // LED3# -#define IOMUX_GPIO_64 0x47 // PE3_WDIS +#define IOMUX_GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5) #define IOMUX_GPIO_66 0x5B // SPKR -#define IOMUX_GPIO_68 0x48 // PE4_WDIS +#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) #define IOMUX_GPIO_71 0x4D // PROCHOT -#define GPIO_32 0x164 // MODESW +#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5) +#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5) #define GPIO_49 0x100 // STRAP0 #define GPIO_50 0x104 // STRAP1 -#define GPIO_51 0x108 // PE3 Reset -#define GPIO_55 0x10C // PE4 Reset +#define GPIO_51 0x108 // PE3 Reset (SIM1 Reset on APU5) +#define GPIO_55 0x10C // PE4 Reset (SIM2 Reset on APU5) #define GPIO_57 0x110 // LED1# #define GPIO_58 0x114 // LED2# #define GPIO_59 0x118 // LED3# -#define GPIO_64 0x11C // PE3_WDIS +#define GPIO_64 0x11C // PE3_WDIS (SIM3 Reset on APU5) #define GPIO_66 0x16C // SPKR -#define GPIO_68 0x120 // PE4_WDIS +#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5) #define GPIO_71 0x134 // PROCHOT #define GPIO_OUTPUT_ENABLE 23 diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 9eb9e817d0..14335185b8 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -116,7 +116,12 @@ static void early_lpc_init(void) // // Configure output disabled, value low, pull up/down disabled // - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting); + if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) || + IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) { + configure_gpio(ACPI_MMIO_BASE, + IOMUX_GPIO_32, Function0, GPIO_32, setting); + } + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting); configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting); configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting); @@ -124,6 +129,11 @@ static void early_lpc_init(void) // Configure output enabled, value low, pull up/down disabled // setting = 0x1 << GPIO_OUTPUT_ENABLE; + if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) { + configure_gpio(ACPI_MMIO_BASE, + IOMUX_GPIO_33, Function0, GPIO_33, setting); + } + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting); configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting); configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting); @@ -131,6 +141,13 @@ static void early_lpc_init(void) // Configure output enabled, value high, pull up/down disabled // setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE; + if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { + configure_gpio(ACPI_MMIO_BASE, + IOMUX_GPIO_32, Function0, GPIO_32, setting); + configure_gpio(ACPI_MMIO_BASE, + IOMUX_GPIO_33, Function0, GPIO_33, setting); + } + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting); configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting); configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting); diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 4f3206408e..4f3206408e 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb new file mode 100644 index 0000000000..880f3dd9c8 --- /dev/null +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -0,0 +1,94 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00730F01 + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.2 on end # LAN3 + device pci 2.3 on end # LAN2 + device pci 2.4 on end # LAN1 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI0 usb[0:3] is connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM + end # LPC 0x439d + + device pci 14.7 on end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00730F01/root_complex diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb new file mode 100644 index 0000000000..4bdaaaf834 --- /dev/null +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -0,0 +1,93 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00730F01 + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # mPCIe slot 2 (on GFX lane) + device pci 2.2 on end # LAN3 + device pci 2.3 on end # LAN2 + device pci 2.4 on end # LAN1 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI0 usb[0:3] is connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + device pnp 2e.007 off end + device pnp 2e.107 off end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM + end # LPC 0x439d + + device pci 14.7 off end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00730F01/root_complex |