diff options
Diffstat (limited to 'src/mainboard/pcengines/apu2/romstage.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 50 |
1 files changed, 4 insertions, 46 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 3e2672ad70..27f0183787 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -14,62 +14,21 @@ */ #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <device/pnp.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> -#include <Fch/Fch.h> #include "gpio_ftns.h" -#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - static void early_lpc_init(void); void board_BeforeAgesa(struct sysinfo *cb) { u32 val; - pci_devfn_t dev; - u32 data; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xd2, 0xcd6); - outb(0x00, 0xcd7); - - post_code(0x30); - early_lpc_init(); - - hudson_clk_output_48Mhz(); - post_code(0x31); - - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); + early_lpc_init(); /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); @@ -78,9 +37,8 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); } - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); + /* Release GPIO32/33 for other uses. */ + pm_write8(0xea, 1); } static void early_lpc_init(void) |