1 files changed, 60 insertions, 69 deletions

diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index dff346e16a..264dd77835 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -17,6 +17,7 @@
 #include <console/console.h>
 #include <spd_bin.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <FchPlatform.h>
 #include <stdlib.h>
 
@@ -24,7 +25,6 @@
 #include "imc.h"
 #include "hudson.h"
 
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
@@ -35,8 +35,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
 	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
 	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config }
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
@@ -57,75 +56,67 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
 	FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;                /* 1 enable, 0 disable TSI Auto Polling */
 }
 
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams)
 {
-	AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams =  (FCH_RESET_DATA_BLOCK *) FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-		//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
-		FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
-		FchParams->FchReset.SataEnable = hudson_sata_enable();
-		FchParams->FchReset.IdeEnable = hudson_ide_enable();
-		FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->FchReset.Xhci1Enable = FALSE;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
-
-		FchParams->Azalia.AzaliaEnable = AzDisable;
-
-		/* Fan Control */
-		oem_fan_control(FchParams);
-
-		/* XHCI configuration */
-		FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->Usb.Xhci1Enable = FALSE;
-
-		/* EHCI configuration */
-		FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
-
-		if (CONFIG(BOARD_PCENGINES_APU2)) {
-			// Disable EHCI 0 (port 0 to 3)
-			FchParams->Usb.Ehci1Enable = FALSE;
-		} else {
-			// Enable EHCI 0 (port 0 to 3)
-			FchParams->Usb.Ehci1Enable = TRUE;
-		}
-
-		// Enable EHCI 1 (port 4 to 7)
-		// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
-		FchParams->Usb.Ehci2Enable = TRUE;
-
-		/* sata configuration */
-		FchParams->Sata.SataDevSlpPort0 = 0;	// Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
-		FchParams->Sata.SataDevSlpPort1 = 0;
-
-		FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
-		switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
-		case SataRaid:
-		case SataAhci:
-		case SataAhci7804:
-		case SataLegacyIde:
-			FchParams->Sata.SataIdeMode = FALSE;
-			break;
-		case SataIde2Ahci:
-		case SataIde2Ahci7804:
-		default: /* SataNativeIde */
-			FchParams->Sata.SataIdeMode = TRUE;
-			break;
-		}
-	}
+	printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+	//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+	FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
+	FchParams->FchReset.SataEnable = hudson_sata_enable();
+	FchParams->FchReset.IdeEnable = hudson_ide_enable();
+	FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchParams->FchReset.Xhci1Enable = FALSE;
 	printk(BIOS_DEBUG, "Done\n");
+}
 
-	return AGESA_SUCCESS;
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
+{
+	printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+
+	FchParams->Azalia.AzaliaEnable = AzDisable;
+
+	/* Fan Control */
+	oem_fan_control(FchParams);
+
+	/* XHCI configuration */
+	FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchParams->Usb.Xhci1Enable = FALSE;
+
+	/* EHCI configuration */
+	FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
+
+	if (CONFIG(BOARD_PCENGINES_APU2)) {
+		// Disable EHCI 0 (port 0 to 3)
+		FchParams->Usb.Ehci1Enable = FALSE;
+	} else {
+		// Enable EHCI 0 (port 0 to 3)
+		FchParams->Usb.Ehci1Enable = TRUE;
+	}
+
+	// Enable EHCI 1 (port 4 to 7)
+	// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+	FchParams->Usb.Ehci2Enable = TRUE;
+
+	/* sata configuration */
+	// Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+	FchParams->Sata.SataDevSlpPort0 = 0;
+	FchParams->Sata.SataDevSlpPort1 = 0;
+
+	FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+	switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+	case SataRaid:
+	case SataAhci:
+	case SataAhci7804:
+	case SataLegacyIde:
+		FchParams->Sata.SataIdeMode = FALSE;
+		break;
+	case SataIde2Ahci:
+	case SataIde2Ahci7804:
+	default: /* SataNativeIde */
+		FchParams->Sata.SataIdeMode = TRUE;
+		break;
+	}
+	printk(BIOS_DEBUG, "Done\n");
 }
 
 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)