diff options
Diffstat (limited to 'src/mainboard/pcengines/apu1/devicetree.cb')
| -rw-r--r-- | src/mainboard/pcengines/apu1/devicetree.cb | 62 |
1 files changed, 39 insertions, 23 deletions
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 2f6bb14fc8..5f6f9c9ee7 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Kyösti Mälkki <kyosti.malkki@gmail.com> # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -28,44 +29,65 @@ chip northbridge/amd/agesa/family14/root_complex # device pci 18.0 on # northbridge chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge + device pci 7.0 on end # PCIE P2P bridge + device pci 8.0 on end # NB/SB Link P2P bridge end # agesa northbridge chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # OHCI USB 0-4 + device pci 12.1 on end # OHCI USB 0-4 device pci 12.2 on end # EHCI USB 0-4 device pci 13.0 on end # OHCI USB 5-9 + device pci 13.1 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 off + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 off + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + device pnp 2e.7 off end + device pnp 2e.107 off end + device pnp 2e.607 off end + device pnp 2e.e off end + end end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA + device pci 14.5 on end # OHCI FS/LS USB + #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "0" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 # end # device pci 18.0 # These seem unnecessary @@ -78,12 +100,6 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.6 on end device pci 18.7 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex |