diff options
Diffstat (limited to 'src/mainboard/pcengines/alix1c')
| -rw-r--r-- | src/mainboard/pcengines/alix1c/Config.lb | 34 |
1 files changed, 1 insertions, 33 deletions
diff --git a/src/mainboard/pcengines/alix1c/Config.lb b/src/mainboard/pcengines/alix1c/Config.lb index 89cb42ad79..ca4642bb40 100644 --- a/src/mainboard/pcengines/alix1c/Config.lb +++ b/src/mainboard/pcengines/alix1c/Config.lb @@ -18,39 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +include /config/nofailovercalculation.lb ## ## Set all of the defaults for an x86 architecture |