diff options
Diffstat (limited to 'src/mainboard/pcengines/alix1c/romstage.c')
| -rw-r--r-- | src/mainboard/pcengines/alix1c/romstage.c | 24 |
1 files changed, 5 insertions, 19 deletions
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index c4a9cc98e5..a9b6db5a6c 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -115,31 +115,14 @@ static u8 spd_read_byte(u8 device, u8 address) #include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c" - -static void msr_init(void) -{ - msr_t msr; - - /* Setup access to the MC for under 1MB. Note MC not setup yet. */ - msr.hi = 0x24fffc02; - msr.lo = 0x10010000; - wrmsr(CPU_RCONF_DEFAULT, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff00; - wrmsr(MSR_GLIU0 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff00; - wrmsr(MSR_GLIU1 + 0x20, msr); -} +#include "cpu/amd/model_lx/msrinit.c" /** Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) { } -void cache_as_ram_main(void) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { {.channel0 = {0x50}}, @@ -161,6 +144,9 @@ void cache_as_ram_main(void) uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(ManualConf); cpuRegInit(); |