diff options
Diffstat (limited to 'src/mainboard/olpc/btest')
| -rw-r--r-- | src/mainboard/olpc/btest/Kconfig | 26 | ||||
| -rw-r--r-- | src/mainboard/olpc/btest/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/olpc/btest/chip.h | 3 | ||||
| -rw-r--r-- | src/mainboard/olpc/btest/cmos.layout | 75 | ||||
| -rw-r--r-- | src/mainboard/olpc/btest/devicetree.cb | 44 | ||||
| -rw-r--r-- | src/mainboard/olpc/btest/irq_tables.c | 31 | ||||
| -rw-r--r-- | src/mainboard/olpc/btest/mainboard.c | 137 | ||||
| -rw-r--r-- | src/mainboard/olpc/btest/romstage.c | 182 |
8 files changed, 0 insertions, 499 deletions
diff --git a/src/mainboard/olpc/btest/Kconfig b/src/mainboard/olpc/btest/Kconfig deleted file mode 100644 index a8405e2ee4..0000000000 --- a/src/mainboard/olpc/btest/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -if BOARD_OLPC_BTEST - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_AMD_GX2 - select NORTHBRIDGE_AMD_GX2 - select SOUTHBRIDGE_AMD_CS5536 - select UDELAY_TSC - select CACHE_AS_RAM - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default olpc/btest - -config MAINBOARD_PART_NUMBER - string - default "btest" - -config IRQ_SLOT_COUNT - int - default 2 - -endif # BOARD_OLPC_BTEST diff --git a/src/mainboard/olpc/btest/Makefile.inc b/src/mainboard/olpc/btest/Makefile.inc deleted file mode 100644 index aa29c17dc1..0000000000 --- a/src/mainboard/olpc/btest/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS=-mcpu=p2 -O diff --git a/src/mainboard/olpc/btest/chip.h b/src/mainboard/olpc/btest/chip.h deleted file mode 100644 index d138e51b94..0000000000 --- a/src/mainboard/olpc/btest/chip.h +++ /dev/null @@ -1,3 +0,0 @@ -extern struct chip_operations mainboard_ops; - -struct mainboard_config {}; diff --git a/src/mainboard/olpc/btest/cmos.layout b/src/mainboard/olpc/btest/cmos.layout deleted file mode 100644 index 864d89ad2a..0000000000 --- a/src/mainboard/olpc/btest/cmos.layout +++ /dev/null @@ -1,75 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 1 e 0 dcon_present -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 1007 1008 - - diff --git a/src/mainboard/olpc/btest/devicetree.cb b/src/mainboard/olpc/btest/devicetree.cb deleted file mode 100644 index 6fec1f0184..0000000000 --- a/src/mainboard/olpc/btest/devicetree.cb +++ /dev/null @@ -1,44 +0,0 @@ -chip northbridge/amd/gx2 - register "irqmap" = "0xaa5b" - device lapic_cluster 0 on - chip cpu/amd/model_gx2 - device lapic 0 on end - end - end - device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536 - # 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080. - # Frame Pulse Width = 4clocks - # IRQ Data Frames = 17Frames - # SIRQ Mode = continous , It would be better if the EC could operate in - # Active(Quiet) mode. Save power.... - # SIRQ Enable = Enabled - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - #register "lpc_irq" = "0x00001002" - #register "lpc_serirq_enable" = "0xEFFD0080" - #register "enable_gpio0_inta" = "1" - #register "enable_ide_nand_flash" = "1" - #register "enable_uarta" = "1" - #register "enable_USBP4_host" = "1" - #register "audio_irq" = "5" - #register "usbf4_irq" = "10" - #register "usbf5_irq" = "10" - #register "usbf6_irq" = "0" - #register "usbf7_irq" = "0" - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC - register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG - register "unwanted_vpci[2]" = "0" # End of list has a zero - end - end -end - diff --git a/src/mainboard/olpc/btest/irq_tables.c b/src/mainboard/olpc/btest/irq_tables.c deleted file mode 100644 index adbe0d1acb..0000000000 --- a/src/mainboard/olpc/btest/irq_tables.c +++ /dev/null @@ -1,31 +0,0 @@ -/* This file was generated by getpir.c, do not modify! - (but if you do, please run checkpir on it to verify) - * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up - * - * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM -*/ - -#include <arch/pirq_routing.h> - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0x800, /* IRQs devoted exclusively to PCI usage */ - 0x1078, /* Vendor */ - 0x2, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/olpc/btest/mainboard.c b/src/mainboard/olpc/btest/mainboard.c deleted file mode 100644 index c6b86ef18d..0000000000 --- a/src/mainboard/olpc/btest/mainboard.c +++ /dev/null @@ -1,137 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> -#include <pc80/mc146818rtc.h> -#include "chip.h" -#include "southbridge/amd/cs5536/cs5536_smbus2.h" -#include <cpu/amd/vr.h> - -/* Borrowed from mc146818rtc.c */ - -#define CMOS_READ(addr) ({ \ - outb((addr),RTC_PORT(0)); \ - inb(RTC_PORT(1)); \ - }) - -#define CMOS_WRITE(val, addr) ({ \ - outb((addr),RTC_PORT(0)); \ - outb((val),RTC_PORT(1)); \ - }) - -static void write_bit(unsigned char val) { - - unsigned char byte = CMOS_READ(440 / 8); - - /* Don't change it if its already set */ - - if ((byte & 1) == (val & 1)) - return; - - byte &= ~1; - byte |= val & 1; - CMOS_WRITE(val, 440/8); -} - -static unsigned short _getsmbusbase(void) { - unsigned devfn = PCI_DEVFN(0xf, 0); - device_t dev = dev_find_slot(0x0, devfn); - unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - - return (unsigned short) (addr & ~1); -} - -static void init_dcon(void) { - - int ret = 1; - unsigned short rev = 0; - unsigned short iobase = _getsmbusbase(); - - printk(BIOS_DEBUG, "CHECKING FOR DCON (%x)\n", iobase); - - /* Get the IO base for the SMBUS */ - - rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00); - - if (rev & 0xDC00) { - printk(BIOS_DEBUG, "DCON FOUND - REV %x\n", rev); - - /* Enable the DCON */ - ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069); - if (ret != 0) - printk(BIOS_DEBUG, "DCON ENABLE FAILED %d\n", ret); - } - else - printk(BIOS_DEBUG, "DCON NOT FOUND (%x)\n", rev); - - write_bit(rev > 0 ? 1 : 0); -} - -static void -init_cafe_irq(void){ - const unsigned char slots_cafe[4] = {11, 0, 0, 0}; - - - /* CAFE PCI slots */ - pci_assign_irqs(0, 0x0C, slots_cafe); - - /* Make the pin assignments - NOTENOTENOTE: This should be - * configurable! - */ - - /* Configure the GPIO pins to use - class 0, index 9 to configure - * AB. Write 0xFF to disable - */ - - vrWrite(0x9, 0XFF00); - - /* Configure the GPIO pins to use - class 0, index A to configure - * CD. Write 0xFF to disable - */ - - vrWrite(0xA, 0xFFFF); - -} - - -static void init(struct device *dev) { -/* - unsigned bus = 0; - unsigned devfn = PCI_DEVFN(0xf, 4); - device_t usb = NULL; - unsigned char usbirq = 0xa; -*/ - - printk(BIOS_DEBUG, "OLPC BTEST ENTER %s\n", __func__); - -#if 0 - /* I can't think of any reason NOT to just set this. If it turns out we want this to be - * conditional we can make it a config variable later. - */ - - printk(BIOS_DEBUG, "%s (%x,%x)SET USB PCI interrupt line to %d\n", - __func__, bus, devfn, usbirq); - usb = dev_find_slot(bus, devfn); - if (! usb){ - printk(BIOS_ERR, "Could not find USB\n"); - } else { - pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq); - } -#endif - - init_dcon(); - init_cafe_irq(); - printk(BIOS_DEBUG, "OLPC BTEST EXIT %s\n", __func__); -} - -static void enable_dev(struct device *dev) -{ - dev->ops->init = init; -} - -struct chip_operations mainboard_ops = { - CHIP_NAME("OLPC btest Mainboard") - .enable_dev = enable_dev, -}; diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c deleted file mode 100644 index 7f8779f720..0000000000 --- a/src/mainboard/olpc/btest/romstage.c +++ /dev/null @@ -1,182 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/hlt.h> -#include <console/console.h> -#include "lib/ramtest.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" -#include <cpu/amd/gx2def.h> -#include <cpu/amd/geode_post_code.h> - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/gx2/raminit.h" - -static inline unsigned int fls(unsigned int x) -{ - int r; - - __asm__("bsfl %1,%0\n\t" - "jnz 1f\n\t" - "movl $32,%0\n" - "1:" : "=r" (r) : "g" (x)); - return r; -} - -/* sdram parameters for OLPC: - row address = 13 - col address = 9 - banks = 4 - dimm0size=128MB - d0_MB=1 (module banks) - d0_cb=4 (component banks) - do_psz=4KB (page size) - Trc=10 (clocks) (ref2act) - Tras=7 (act2pre) - Trcd=3 (act2cmd) - Trp=3 (pre2act) - Trrd=2 (act2act) - Tref=17.8ms - */ -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * - * component Banks (byte 17) * module banks, side (byte 5) * - * width in bits (byte 6,7) - * = Density per side (byte 31) * number of sides (byte 5) */ - /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ - msr_t msr; - unsigned char module_banks, val; - - msr = rdmsr(MC_CF07_DATA); - - /* get module banks (sides) per dimm, SPD byte 5 */ - module_banks = 1; - module_banks >>= 1; - msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); - msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); - - /* get component banks per module bank, SPD byte 17 */ - val = 4; - val >>= 2; - msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); - - /* get the module bank density, SPD byte 31 */ - /* this is multiples of 8 MB */ - /* actually it is 2^x*4, where x is the value you put in */ - /* for OLPC, set default size */ - /* dimm size - hardcoded 128Mb */ - val = 5; - msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT); - - /* page size = 2^col address */ - val = 2; /* 4096 bytes */ - msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT); - msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT); - - print_debug("computed msr.hi "); - print_debug_hex32(msr.hi); - print_debug("\n"); - - /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ - /* well, it may be close. It's about 200,000 ticks */ - msr.lo = 0x00003000; - wrmsr(MC_CF07_DATA, msr); - - /* timing and mode ... */ - - msr = rdmsr(0x20000019); - - /* per standard bios settings */ - - msr.hi = 0x18000108; - msr.lo = - (6<<28) | // cas_lat - (10<<24)| // ref2act - (7<<20)| // act2pre - (3<<16)| // pre2act - (3<<12)| // act2cmd - (2<<8)| // act2act - (2<<6)| // dplwr - (2<<4)| // dplrd - (3); // dal - /* the msr value reported by quanta is very, very different. - * we will go with that value for now. - */ - msr.lo = 0x286332a3; - - wrmsr(0x20000019, msr); - -} - -#include "northbridge/amd/gx2/raminit.c" -#include "lib/generic_sdram.c" - -#define PLLMSRhi 0x00001490 -#define PLLMSRlo 0x02000030 -#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) -#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0)) -#include "northbridge/amd/gx2/pll_reset.c" -#include "cpu/amd/model_gx2/cpureginit.c" -#include "cpu/amd/model_gx2/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" - -static void gpio_init(void) -{ - unsigned long m; - - /* Make sure events enable for gpio 12 is off */ - - m = inl(GPIOL_EVENTS_ENABLE); - m &= ~GPIOL_12_SET; - m |= GPIOL_12_CLEAR; - outl(m, GPIOL_EVENTS_ENABLE); -} - -void main(unsigned long bist) -{ - static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} - }; - - SystemPreInit(); - msr_init(); - - cs5536_early_setup(); - - /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536 - */ - cs5536_setup_onchipuart(1); - gpio_init(); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - pll_reset(); - - cpuRegInit(); - print_err("done cpuRegInit\n"); - - sdram_initialize(1, memctrl); - - /* Check all of memory */ - //ram_check(0x00000000, 640*1024); -} - |