diff options
Diffstat (limited to 'src/mainboard/nokia/ip530')
-rw-r--r-- | src/mainboard/nokia/ip530/Kconfig | 52 | ||||
-rw-r--r-- | src/mainboard/nokia/ip530/devicetree.cb | 58 | ||||
-rw-r--r-- | src/mainboard/nokia/ip530/irq_tables.c | 57 | ||||
-rw-r--r-- | src/mainboard/nokia/ip530/mainboard.c | 37 |
4 files changed, 149 insertions, 55 deletions
diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig index 3c869006a7..f7769882ad 100644 --- a/src/mainboard/nokia/ip530/Kconfig +++ b/src/mainboard/nokia/ip530/Kconfig @@ -24,10 +24,12 @@ config BOARD_NOKIA_IP530 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO + select DRIVERS_TI_PCI1225 + select DRIVERS_DEC_21143PD select ROMCC + select PIRQ_ROUTE select HAVE_PIRQ_TABLE select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR string @@ -46,6 +48,52 @@ config HAVE_OPTION_TABLE config IRQ_SLOT_COUNT int - default 6 + default 22 depends on BOARD_NOKIA_IP530 +## Configuration items for the ethernet adaptors +config DEC21143_CACHE_LINE_SIZE + int + default 0x00000000 + depends on BOARD_NOKIA_IP530 + +config DEC21143_EXPANSION_ROM_BASE_ADDRESS + hex + default 0x00000000 + depends on BOARD_NOKIA_IP530 + +config DEC21143_COMMAND_AND_STATUS_CONFIGURATION + hex + default 0x02800107 + depends on BOARD_NOKIA_IP530 + +## Configuration for the PCMCIA-Cardbus controller. +config TI_PCMCIA_CARDBUS_CMDR + hex + default 0x0107 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_CLSR + hex + default 0x00 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_CLTR + hex + default 0x40 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_BCR + hex + default 0x07C0 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_SCR + hex + default 0x08449060 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_MRR + hex + default 0x00007522 + depends on BOARD_NOKIA_IP530 diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index ebccad0d46..cc3fd37e11 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -30,16 +30,8 @@ chip northbridge/intel/i440bx # Northbridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end + device pnp 3f0.0 off end # Floppy (No connector) + device pnp 3f0.3 off end # Parallel port (No connector) device pnp 3f0.4 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 @@ -48,47 +40,23 @@ chip northbridge/intel/i440bx # Northbridge io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.9 on # Game port - io 0x60 = 0x201 - end - device pnp 3f0.a on # Power-management events (PME) - io 0x60 = 0x600 - end - device pnp 3f0.b on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 5 - end + device pnp 3f0.7 on end # PS/2 keyboard / mouse + device pnp 3f0.6 on end # RTC + device pnp 3f0.8 on end # AUX I/O + device pnp 3f0.A off end # ACPI (No support yet) end end device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.2 off end # USB (No connector) + device pci 7.3 off end # ACPI (No support yet) register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" + # Disable UDMA/33 for lower speed if your IDE device(s) don't support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" end - device pci 0d.0 on end # NIC (DEC DECchip 21142/43) - device pci 0e.0 on end # NIC (DEC DECchip 21142/43) - device pci 0f.0 on end # CardBus bridge (TI PCI1225) - device pci 0f.1 on end # CardBus bridge (TI PCI1225) - end - device pci_domain 1 on # PCI domain 1 - device pci 00.0 on end # PCI bridge (DEC DECchip 21150) - end - device pci_domain 2 on # PCI domain 2 - device pci 04.0 on end # NIC (DECchip 21142/43) - device pci 04.0 on end # NIC (DECchip 21142/43) end end - diff --git a/src/mainboard/nokia/ip530/irq_tables.c b/src/mainboard/nokia/ip530/irq_tables.c index ae2d420289..d5f4cb4da4 100644 --- a/src/mainboard/nokia/ip530/irq_tables.c +++ b/src/mainboard/nokia/ip530/irq_tables.c @@ -31,15 +31,46 @@ const struct irq_routing_table intel_irq_routing_table = { 0x122e, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x36, /* Checksum */ + 0x44, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0}, - {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0}, - {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0}, + /** + * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller. + */ + // Southbridge 82371 + { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 }, + // On-board PCI-to-PCI bridge + { 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 }, + // ETH1 on front panel + { 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // ETH2 on front panel + { 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // ETH3 on front panel + { 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // ETH4 on front panel + { 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // PCMCIA/Cardbus controller + { 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // Bridge for slot 1 (top) + { 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 }, + // PCI compact slots 1 (top) + { 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 }, + { 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 }, + { 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 }, + { 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 }, + // Bridge for slot 2 (middle) + { 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 }, + // PCI compact slots 2 (middle) + { 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 }, + { 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 }, + { 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 }, + { 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 }, + // Bridge for slot 3 (bottom) + { 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 }, + // PCI compact slots 3 (bottom) + { 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 }, + { 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 }, + { 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 }, + { 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 }, } }; @@ -47,3 +78,13 @@ unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr); } + +/** + * TODO: This stub function is here until the point is solved in the + * main code of coreboot. see also arch/i386/boot/pirq_tables.c + */ +void pirq_assign_irqs(const unsigned char pIntAtoD[4]) +{ + return; +} + diff --git a/src/mainboard/nokia/ip530/mainboard.c b/src/mainboard/nokia/ip530/mainboard.c index b0dd27bdb8..61537c8be8 100644 --- a/src/mainboard/nokia/ip530/mainboard.c +++ b/src/mainboard/nokia/ip530/mainboard.c @@ -20,7 +20,44 @@ #include <device/device.h> #include "chip.h" +#include <device/pci_def.h> +#include <device/pci.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#define OUTB outb +#define INB inb + +/* +* Taken from flashrom project +* Generic Super I/O helper functions +*/ +static uint8_t sio_read(uint16_t port, uint8_t reg) +{ + OUTB( reg, port ); + return ( INB( port + 1 ) ); +} + +static void sio_write(uint16_t port, uint8_t reg, uint8_t data) +{ + OUTB( reg, port ); + OUTB( data, port + 1 ); + return; +} + +static void nokia_ip530_board_enable( device_t dev ) +{ + print_debug( "Setting up IP530-Super I/O devices\n"); + sio_write( 0x20, 0x03, 0x80 ); + printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) ); + sio_write( 0x20, 0x22, 0x30 ); + printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) ); + sio_write( 0x20, 0x24, 0x84 ); + printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) ); + return; +} struct chip_operations mainboard_ops = { CHIP_NAME("Nokia IP530 Mainboard") + .enable_dev = nokia_ip530_board_enable, }; |