diff options
Diffstat (limited to 'src/mainboard/newisys')
| -rw-r--r-- | src/mainboard/newisys/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/newisys/khepri/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/newisys/khepri/resourcemap.c | 6 | ||||
| -rw-r--r-- | src/mainboard/newisys/khepri/romstage.c | 10 |
4 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/newisys/Kconfig b/src/mainboard/newisys/Kconfig index fd8f9176e1..308cced541 100644 --- a/src/mainboard/newisys/Kconfig +++ b/src/mainboard/newisys/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_NEWISYS - + source "src/mainboard/newisys/khepri/Kconfig" endchoice diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb index cb8f356e5a..30e73f774d 100644 --- a/src/mainboard/newisys/khepri/devicetree.cb +++ b/src/mainboard/newisys/khepri/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 + device pci 18.0 on end # LDT 0 device pci 18.0 on # LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end @@ -57,7 +57,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -69,7 +69,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on end + device pci 1.3 on end device pci 1.5 on end device pci 1.6 on end end @@ -87,6 +87,6 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end end diff --git a/src/mainboard/newisys/khepri/resourcemap.c b/src/mainboard/newisys/khepri/resourcemap.c index d533b6357e..81bdefa835 100644 --- a/src/mainboard/newisys/khepri/resourcemap.c +++ b/src/mainboard/newisys/khepri/resourcemap.c @@ -151,7 +151,7 @@ static void setup_khepri_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -207,7 +207,7 @@ static void setup_khepri_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -215,7 +215,7 @@ static void setup_khepri_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index e8c040950f..bf1186df46 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -1,10 +1,10 @@ /* * This code is derived from the Tyan s2882 romstage.c * Adapted by Stefan Reinauer <stepan@coresystems.de> - * Additional (C) 2007 coresystems GmbH + * Additional (C) 2007 coresystems GmbH */ - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -81,7 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* newisys khepri does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -129,13 +129,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } // post_code(0x32); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); |