diff options
Diffstat (limited to 'src/mainboard/msi/ms7135')
| -rw-r--r-- | src/mainboard/msi/ms7135/Config.lb | 40 | ||||
| -rw-r--r-- | src/mainboard/msi/ms7135/Options.lb | 228 | ||||
| -rw-r--r-- | src/mainboard/msi/ms7135/cache_as_ram_auto.c | 24 |
3 files changed, 146 insertions, 146 deletions
diff --git a/src/mainboard/msi/ms7135/Config.lb b/src/mainboard/msi/ms7135/Config.lb index d316182ebd..5bd867b888 100644 --- a/src/mainboard/msi/ms7135/Config.lb +++ b/src/mainboard/msi/ms7135/Config.lb @@ -22,8 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -39,23 +39,23 @@ driver mainboard.o # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end @@ -64,13 +64,13 @@ end ## ## Build our 16 bit and 32 bit coreboot entry code. ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -86,8 +86,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (this is where coreboot is entered). ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -95,7 +95,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -113,13 +113,13 @@ ldscript /southbridge/nvidia/ck804/id.lds ## ## ROMSTRAP table for CK804 ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc ldscript /southbridge/nvidia/ck804/romstrap.lds end @@ -135,12 +135,12 @@ end ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb index 36260c76e0..e5f8ead7e5 100644 --- a/src/mainboard/msi/ms7135/Options.lb +++ b/src/mainboard/msi/ms7135/Options.lb @@ -20,102 +20,102 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE +uses CONFIG_RAMBASE uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_BTEXT -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZEK -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_AP_CODE_IN_CAR uses CONFIG_USE_PRINTK_IN_CAR -uses MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_MEM_TRAIN_SEQ +uses CONFIG_WAIT_BEFORE_CPUS_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY uses CONFIG_LB_MEM_TOPK -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## ---> 512 Kbytes -default ROM_SIZE=(512*1024) +default CONFIG_ROM_SIZE=(512*1024) ## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=(252*1024) +default CONFIG_FALLBACK_SIZE=(252*1024) #FAILOVER: 4K -default FAILOVER_SIZE=(4*1024) +default CONFIG_FAILOVER_SIZE=(4*1024) ### ### Build options @@ -124,37 +124,37 @@ default FAILOVER_SIZE=(4*1024) ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=13 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -166,19 +166,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 ##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0 +default CONFIG_HT_CHAIN_UNITID_BASE=0 ##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x10 +#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x10 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 @@ -190,22 +190,22 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xcf000 -#default DCACHE_RAM_SIZE=0x1000 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_DCACHE_RAM=1 +#default CONFIG_DCACHE_RAM_BASE=0xcf000 +#default CONFIG_DCACHE_RAM_SIZE=0x1000 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 ## APIC stuff -#default ENABLE_APIC_EXT_ID=0 -#default APIC_ID_OFFSET=0x10 -#default LIFT_BSP_APIC_ID=0 +#default CONFIG_ENABLE_APIC_EXT_ID=0 +#default CONFIG_APIC_ID_OFFSET=0x10 +#default CONFIG_LIFT_BSP_APIC_ID=0 #default CONFIG_PCI_64BIT_PREF_MEM=1 @@ -218,39 +218,39 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" -default MAINBOARD_VENDOR="MSI" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 +default CONFIG_MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)" +default CONFIG_MAINBOARD_VENDOR="MSI" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135 ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = (64*1024) +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = (64*1024) #65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +#efault CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM @@ -264,8 +264,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -282,21 +282,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -308,17 +308,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/msi/ms7135/cache_as_ram_auto.c b/src/mainboard/msi/ms7135/cache_as_ram_auto.c index eaeeeb16e5..b8a22a97c5 100644 --- a/src/mainboard/msi/ms7135/cache_as_ram_auto.c +++ b/src/mainboard/msi/ms7135/cache_as_ram_auto.c @@ -50,7 +50,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 /* Used by ck804_early_setup(). */ #define CK804_NUM 1 @@ -101,10 +101,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \ - || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ + || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -169,7 +169,7 @@ normal_image: fallback_image: -#if HAVE_FAILOVER_BOOT == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ @@ -178,27 +178,27 @@ fallback_image: ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT == 1 -#if USE_FAILOVER_IMAGE == 1 +#if CONFIG_HAVE_FAILOVER_BOOT == 1 +#if CONFIG_USE_FAILOVER_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif } -#if USE_FAILOVER_IMAGE == 0 +#if CONFIG_USE_FAILOVER_IMAGE == 0 void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -218,7 +218,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -270,4 +270,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif /* USE_FAILOVER_IMAGE */ +#endif /* CONFIG_USE_FAILOVER_IMAGE */ |