diff options
Diffstat (limited to 'src/mainboard/motorola')
| -rw-r--r-- | src/mainboard/motorola/sandpoint/Config.lb | 4 | ||||
| -rw-r--r-- | src/mainboard/motorola/sandpoint/Options.lb | 118 | ||||
| -rw-r--r-- | src/mainboard/motorola/sandpoint/init.c | 10 | ||||
| -rw-r--r-- | src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb | 118 |
4 files changed, 125 insertions, 125 deletions
diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb index ee6abf85fd..5ed46bd3b7 100644 --- a/src/mainboard/motorola/sandpoint/Config.lb +++ b/src/mainboard/motorola/sandpoint/Config.lb @@ -15,7 +15,7 @@ initobject clock.o object clock.o ## -## Set our ARCH +## Set our CONFIG_ARCH ## arch ppc end @@ -26,5 +26,5 @@ arch ppc end dir nvram dir flash -addaction coreboot.a "$(CROSS_COMPILE)ranlib coreboot.a" +addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a" makedefine CFLAGS += -g diff --git a/src/mainboard/motorola/sandpoint/Options.lb b/src/mainboard/motorola/sandpoint/Options.lb index 239ebc4a08..7d50c39ce1 100644 --- a/src/mainboard/motorola/sandpoint/Options.lb +++ b/src/mainboard/motorola/sandpoint/Options.lb @@ -5,70 +5,70 @@ uses CONFIG_SANDPOINT_TALUS uses CONFIG_SANDPOINT_UNITY uses CONFIG_SANDPOINT_VALIS uses CONFIG_SANDPOINT_GYRUS -uses ISA_IO_BASE -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses PNP_CFGADDR -uses PNP_CFGDATA -uses _IO_BASE - -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_IO_BASE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_PNP_CFGADDR +uses CONFIG_PNP_CFGDATA +uses CONFIG_IO_BASE + +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CHIP_CONFIGURE -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT -uses AUTOBOOT_CMDLINE -uses PAYLOAD_SIZE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0xfe000000 -default ISA_MEM_BASE=0xfd000000 -default PCIC0_CFGADDR=0xfec00000 -default PCIC0_CFGDATA=0xfee00000 -default PNP_CFGADDR=0x15c -default PNP_CFGDATA=0x15d -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xfe000000 +default CONFIG_ISA_MEM_BASE=0xfd000000 +default CONFIG_PCIC0_CFGADDR=0xfec00000 +default CONFIG_PCIC0_CFGDATA=0xfee00000 +default CONFIG_PNP_CFGADDR=0x15c +default CONFIG_PNP_CFGDATA=0x15d +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" default CONFIG_ARCH_X86=0 ## Use stage 1 initialization code @@ -81,12 +81,12 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## Load payload using filo default CONFIG_IDE=1 @@ -94,34 +94,34 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hdc1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz" # coreboot must fit into 128KB -default ROM_IMAGE_SIZE=131072 -default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} -default PAYLOAD_SIZE=262144 +default CONFIG_ROM_IMAGE_SIZE=131072 +default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE} +default CONFIG_PAYLOAD_SIZE=262144 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 default CONFIG_SANDPOINT_ALTIMUS=1 diff --git a/src/mainboard/motorola/sandpoint/init.c b/src/mainboard/motorola/sandpoint/init.c index 567a6aed70..42acd35164 100644 --- a/src/mainboard/motorola/sandpoint/init.c +++ b/src/mainboard/motorola/sandpoint/init.c @@ -38,8 +38,8 @@ void pnp_output(char address, char data) { - outb(address, PNP_CFGADDR); - outb(data, PNP_CFGDATA); + outb(address, CONFIG_PNP_CFGADDR); + outb(data, CONFIG_PNP_CFGDATA); } void @@ -55,10 +55,10 @@ board_init(void) */ pnp_output(0x07, 6); /* LD 6 = UART0 */ pnp_output(0x30, 0); /* Dectivate */ - pnp_output(0x60, TTYS0_BASE >> 8); /* IO Base */ - pnp_output(0x61, TTYS0_BASE & 0xFF); /* IO Base */ + pnp_output(0x60, CONFIG_TTYS0_BASE >> 8); /* IO Base */ + pnp_output(0x61, CONFIG_TTYS0_BASE & 0xFF); /* IO Base */ pnp_output(0x30, 1); /* Activate */ - uart8250_init(TTYS0_BASE, 115200/TTYS0_BAUD, TTYS0_LCS); + uart8250_init(CONFIG_TTYS0_BASE, 115200/CONFIG_TTYS0_BAUD, CONFIG_TTYS0_LCS); } void diff --git a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb index 42b183f916..1a47974bf8 100644 --- a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb +++ b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb @@ -1,22 +1,22 @@ -uses ISA_IO_BASE +uses CONFIG_ISA_IO_BASE uses CONFIG_CBFS -uses ISA_MEM_BASE -uses PCIC0_CFGADDR -uses PCIC0_CFGDATA -uses PNP_CFGADDR -uses PNP_CFGDATA -uses _IO_BASE - -uses CROSS_COMPILE -uses HAVE_OPTION_TABLE +uses CONFIG_ISA_MEM_BASE +uses CONFIG_PCIC0_CFGADDR +uses CONFIG_PCIC0_CFGDATA +uses CONFIG_PNP_CFGADDR +uses CONFIG_PNP_CFGDATA +uses CONFIG_IO_BASE + +uses CONFIG_CROSS_COMPILE +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_SANDPOINT_ALTIMUS uses CONFIG_COMPRESS -uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_USE_INIT uses CONFIG_CHIP_CONFIGURE -uses NO_POST +uses CONFIG_NO_POST uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BASE +uses CONFIG_TTYS0_BASE uses CONFIG_IDE uses CONFIG_FS_PAYLOAD uses CONFIG_FS_EXT2 @@ -24,47 +24,47 @@ uses CONFIG_FS_ISO9660 uses CONFIG_FS_FAT uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses AUTOBOOT_CMDLINE -uses PAYLOAD_SIZE -uses ROM_SIZE -uses ROM_IMAGE_SIZE -uses _RESET -uses _EXCEPTION_VECTORS -uses _ROMBASE -uses _ROMSTART -uses _RAMBASE -uses _RAMSTART -uses STACK_SIZE -uses HEAP_SIZE - -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_AUTOBOOT_CMDLINE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_RESET +uses CONFIG_EXCEPTION_VECTORS +uses CONFIG_ROMBASE +uses CONFIG_ROMSTART +uses CONFIG_RAMBASE +uses CONFIG_RAMSTART +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE + +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY ## ## Set memory map ## -default ISA_IO_BASE=0xfe000000 -default ISA_MEM_BASE=0xfd000000 -default PCIC0_CFGADDR=0xfec00000 -default PCIC0_CFGDATA=0xfee00000 -default PNP_CFGADDR=0x15c -default PNP_CFGDATA=0x15d -default _IO_BASE=ISA_IO_BASE +default CONFIG_ISA_IO_BASE=0xfe000000 +default CONFIG_ISA_MEM_BASE=0xfd000000 +default CONFIG_PCIC0_CFGADDR=0xfec00000 +default CONFIG_PCIC0_CFGDATA=0xfee00000 +default CONFIG_PNP_CFGADDR=0x15c +default CONFIG_PNP_CFGDATA=0x15d +default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc" +default CONFIG_HOSTCC="gcc" ## use a cross compiler -#default CROSS_COMPILE="powerpc-eabi-" -#default CROSS_COMPILE="ppc_74xx-" +#default CONFIG_CROSS_COMPILE="powerpc-eabi-" +#default CONFIG_CROSS_COMPILE="ppc_74xx-" ## Use stage 1 initialization code default CONFIG_USE_INIT=1 @@ -76,12 +76,12 @@ default CONFIG_CHIP_CONFIGURE=1 default CONFIG_COMPRESS=0 ## Turn off POST codes -default NO_POST=1 +default CONFIG_NO_POST=1 ## Enable serial console -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 ## Load payload using filo default CONFIG_IDE=1 @@ -89,34 +89,34 @@ default CONFIG_FS_PAYLOAD=1 default CONFIG_FS_EXT2=1 default CONFIG_FS_ISO9660=1 default CONFIG_FS_FAT=1 -default AUTOBOOT_CMDLINE="hdc1:/vmlinuz" +default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz" # coreboot must fit into 128KB -default ROM_IMAGE_SIZE=131072 -default ROM_SIZE={ROM_IMAGE_SIZE+PAYLOAD_SIZE} -default PAYLOAD_SIZE=262144 +default CONFIG_ROM_IMAGE_SIZE=131072 +default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE} +default CONFIG_PAYLOAD_SIZE=262144 # Set stack and heap sizes (stage 2) -default STACK_SIZE=0x10000 -default HEAP_SIZE=0x10000 +default CONFIG_STACK_SIZE=0x10000 +default CONFIG_HEAP_SIZE=0x10000 # Sandpoint Demo Board ## Base of ROM -default _ROMBASE=0xfff00000 +default CONFIG_ROMBASE=0xfff00000 ## Sandpoint reset vector -default _RESET=_ROMBASE+0x100 +default CONFIG_RESET=CONFIG_ROMBASE+0x100 ## Exception vectors (other than reset vector) -default _EXCEPTION_VECTORS=_RESET+0x100 +default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100 ## Start of coreboot in the boot rom -## = _RESET + exeception vector table size -default _ROMSTART=_RESET+0x3100 +## = CONFIG_RESET + exeception vector table size +default CONFIG_ROMSTART=CONFIG_RESET+0x3100 ## Coreboot C code runs at this location in RAM -default _RAMBASE=0x00100000 -default _RAMSTART=0x00100000 +default CONFIG_RAMBASE=0x00100000 +default CONFIG_RAMSTART=0x00100000 ### End Options.lb # |