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Diffstat (limited to 'src/mainboard/lippert/toucan-af/mainboard.c')
-rw-r--r--src/mainboard/lippert/toucan-af/mainboard.c72
1 files changed, 72 insertions, 0 deletions
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index 99e1c306a2..27952fa33d 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -17,6 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <stdlib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -29,6 +30,76 @@
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/mtrr.h>
#include "SBPLATFORM.h"
+#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
+
+/* Write data block to slave on SMBUS0. */
+#define SMB0_STATUS ((SMBUS0_BASE_ADDRESS) + 0)
+#define SMB0_CONTROL ((SMBUS0_BASE_ADDRESS) + 2)
+#define SMB0_HOSTCMD ((SMBUS0_BASE_ADDRESS) + 3)
+#define SMB0_ADDRESS ((SMBUS0_BASE_ADDRESS) + 4)
+#define SMB0_DATA0 ((SMBUS0_BASE_ADDRESS) + 5)
+#define SMB0_BLOCKDATA ((SMBUS0_BASE_ADDRESS) + 7)
+static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data)
+{
+ __outbyte(SMB0_STATUS, 0x1E); // clear error status
+ __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out
+ __outbyte(SMB0_HOSTCMD, command); // or destination offset
+ __outbyte(SMB0_DATA0, length); // sent before data
+ __inbyte(SMB0_CONTROL); // reset block data array
+ while (length--)
+ __outbyte(SMB0_BLOCKDATA, *(data++));
+ __outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ
+
+ while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors
+ return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors
+}
+
+static void init(struct device *dev)
+{
+ int i;
+ printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
+
+ /* Init Hudson GPIOs. */
+ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
+ FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
+ FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
+ FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS#
+ FCH_GPIO (197) = 0x28; // = input, disable int. pull-up
+ FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
+ FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
+ FCH_IOMUX( 57) = 1;
+ FCH_GPIO ( 57) = 0x28;
+ FCH_IOMUX( 58) = 1;
+ FCH_GPIO ( 58) = 0x28;
+ FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector
+ FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0
+ FCH_IOMUX(188) = 2;
+ FCH_GPIO (188) = 0x08;
+ FCH_IOMUX(166) = 2;
+ FCH_GPIO (166) = 0x08;
+ // needed to make GPO160 work (Hudson Register Reference section 2.3.6.1)
+ FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01;
+ FCH_IOMUX(160) = 1;
+ FCH_GPIO (160) = 0x08;
+ FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector
+ FCH_IOMUX(190) = 1; // default to inputs with int. PU
+ FCH_IOMUX(191) = 1;
+ FCH_IOMUX(192) = 1;
+ if (!fch_gpio_state(197)) // just in case anyone cares
+ printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
+ printk(BIOS_INFO, "Board revision ID: %u\n",
+ fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
+
+ /* Notify the SMC we're alive and kicking, or after a while it will
+ * effect a power cycle and switch to the alternate BIOS chip.
+ * Should be done as late as possible. */
+ printk(BIOS_INFO, "Sending BIOS alive message\n");
+ const u8 i_am_alive[] = { 0x03 }; //bit2=SEL_DP0: 0=DDI2, 1=LVDS
+ if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive)))
+ printk(BIOS_ERR, "smb_write_blk failed: %d\n", i);
+
+ printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
+}
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -56,6 +127,7 @@ void set_pcie_dereset(void)
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ dev->ops->init = init;
/*
* The mainboard is the first place that we get control in ramstage. Check