diff options
Diffstat (limited to 'src/mainboard/lippert/spacerunner-lx/Options.lb')
| -rw-r--r-- | src/mainboard/lippert/spacerunner-lx/Options.lb | 206 |
1 files changed, 0 insertions, 206 deletions
diff --git a/src/mainboard/lippert/spacerunner-lx/Options.lb b/src/mainboard/lippert/spacerunner-lx/Options.lb deleted file mode 100644 index 5bb104bf9a..0000000000 --- a/src/mainboard/lippert/spacerunner-lx/Options.lb +++ /dev/null @@ -1,206 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 LiPPERT Embedded Computers GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## Based on Options.lb from AMD's DB800 mainboard. - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESS -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEBUG -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_VIDEO_MB -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_PIRQ_ROUTE - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 512*1024 - -### -### Build options -### -default CONFIG_CONSOLE_VGA = 0 -default CONFIG_VIDEO_MB = 8 -default CONFIG_PCI_ROM_RUN = 0 - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT = 1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE = 0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET = 0 - -## Delay timer options -## -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 -default CONFIG_PIRQ_ROUTE = 1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE = 0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 0x08000 -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE = 0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE = 0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250 = 1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD = 115200 -#default CONFIG_TTYS0_BAUD = 57600 -#default CONFIG_TTYS0_BAUD = 38400 -#default CONFIG_TTYS0_BAUD = 19200 -#default CONFIG_TTYS0_BAUD = 9600 -#default CONFIG_TTYS0_BAUD = 4800 -#default CONFIG_TTYS0_BAUD = 2400 -#default CONFIG_TTYS0_BAUD = 1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE = 0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS = 0x3 - -# Compile extra debugging code -default CONFIG_DEBUG = 1 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 - -end |