diff options
Diffstat (limited to 'src/mainboard/lippert/roadrunner-lx/Options.lb')
| -rw-r--r-- | src/mainboard/lippert/roadrunner-lx/Options.lb | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/src/mainboard/lippert/roadrunner-lx/Options.lb b/src/mainboard/lippert/roadrunner-lx/Options.lb index 4c03b2c702..a6be7974c9 100644 --- a/src/mainboard/lippert/roadrunner-lx/Options.lb +++ b/src/mainboard/lippert/roadrunner-lx/Options.lb @@ -3,8 +3,6 @@ ## ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH ## -## Based on Options.lb from AMD's DB800 mainboard. -## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or @@ -20,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## Based on Options.lb from AMD's DB800 mainboard. + uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE @@ -80,71 +80,71 @@ uses DCACHE_RAM_SIZE uses PIRQ_ROUTE ## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 512*1024 +default ROM_SIZE = 512 * 1024 ### ### Build options ### -default CONFIG_CONSOLE_VGA=0 -default CONFIG_VIDEO_MB=8 -default CONFIG_PCI_ROM_RUN=0 +default CONFIG_CONSOLE_VGA = 0 +default CONFIG_VIDEO_MB = 8 +default CONFIG_PCI_ROM_RUN = 0 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default HAVE_FALLBACK_BOOT = 1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default HAVE_MP_TABLE = 0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default HAVE_HARD_RESET = 0 ## Delay timer options ## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=7 -default PIRQ_ROUTE=1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 7 +default PIRQ_ROUTE = 1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=0 +default HAVE_OPTION_TABLE = 0 ### ### coreboot layout values ### ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 +default USE_DCACHE_RAM = 1 +default DCACHE_RAM_BASE = 0xc8000 +default DCACHE_RAM_SIZE = 0x08000 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default STACK_SIZE = 8 * 1024 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default HEAP_SIZE = 16 * 1024 ## ## Only use the option table in a normal image @@ -159,36 +159,36 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" ## ## The Serial Console ## # To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 +default CONFIG_CONSOLE_SERIAL8250 = 1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default TTYS0_BAUD = 115200 +#default TTYS0_BAUD = 57600 +#default TTYS0_BAUD = 38400 +#default TTYS0_BAUD = 19200 +#default TTYS0_BAUD = 9600 +#default TTYS0_BAUD = 4800 +#default TTYS0_BAUD = 2400 +#default TTYS0_BAUD = 1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default TTYS0_BASE = 0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default TTYS0_LCS = 0x3 # Compile extra debugging code -default DEBUG=1 +default DEBUG = 1 ## ### Select the coreboot loglevel @@ -204,8 +204,8 @@ default DEBUG=1 ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default DEFAULT_CONSOLE_LOGLEVEL = 8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default MAXIMUM_CONSOLE_LOGLEVEL = 8 end |