diff options
Diffstat (limited to 'src/mainboard/libretrend/lt1000/devicetree.cb')
| -rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 41 |
1 files changed, 23 insertions, 18 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 2ebc67024e..9599ceccfb 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -97,21 +97,7 @@ chip soc/intel/skylake .voltage_limit = 1520, }" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpClkSrcNumber[0]" = "0" - register "PcieRpClkSrcNumber[3]" = "1" - register "PcieRpClkSrcNumber[4]" = "2" - register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpClkSrcNumber[9]" = "3" - register "PcieRpClkSrcNumber[10]" = "3" - register "PcieRpClkSrcNumber[11]" = "3" # PL2 override 25W register "power_limits_config" = "{ @@ -154,19 +140,38 @@ chip soc/intel/skylake }" register "SataSpeedLimit" = "2" end - device ref pcie_rp3 on end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "1" + end + device ref pcie_rp4 on + register "PcieRpEnable[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + end device ref pcie_rp5 on + register "PcieRpEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "2" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" end device ref pcie_rp6 on end device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "3" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "SSD_M.2 2242/2280" "SlotDataBusWidth4X" end - device ref pcie_rp10 on end - device ref pcie_rp11 on end - device ref pcie_rp12 on end + device ref pcie_rp10 on + register "PcieRpEnable[9]" = "1" + register "PcieRpClkSrcNumber[9]" = "3" + end + device ref pcie_rp11 on + register "PcieRpEnable[10]" = "1" + register "PcieRpClkSrcNumber[10]" = "3" + end + device ref pcie_rp12 on + register "PcieRpEnable[11]" = "1" + register "PcieRpClkSrcNumber[11]" = "3" + end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" |