diff options
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/t60/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t60/romstage.c | 21 | ||||
| -rw-r--r-- | src/mainboard/lenovo/thinkcentre_a58/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/thinkcentre_a58/romstage.c | 14 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 20 |
6 files changed, 19 insertions, 46 deletions
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 70900eae2c..ada50f39ce 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -82,6 +82,10 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x001c1681" + device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 end diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index b003de8926..ac78aae841 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -32,25 +32,11 @@ #include <southbridge/intel/common/pmclib.h> #include "dock.h" -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN - | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN); - - /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); - - /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); - - /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -140,7 +126,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); /* We want early GPIO setup, to be able to detect legacy I/O module */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index ace2bfbff2..5559f7dcfd 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -46,6 +46,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x00fc0a01" + device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 device pci 1c.1 on # PCIe 2: NIC diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 10889a9286..d632d9ddbf 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -42,18 +42,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); - /* Fixed IO decode ranges */ - pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); - /* LPC enable devices */ - pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - /* IO decode range: HWM on 0xa00 */ - pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -62,7 +50,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index b3d87ccb4b..1a914fd009 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -76,6 +76,10 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x001c1681" + device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 end diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 34d8d7a435..1008bb0e22 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -33,24 +33,11 @@ #include <southbridge/intel/common/pmclib.h> #include "dock.h" -static void ich7_enable_lpc(void) +/* Override the default lpc decode ranges */ +static void mb_lpc_decode(void) { - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN - | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN); - /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); - - /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); - - /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -144,7 +131,8 @@ void mainboard_romstage_entry(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */ setup_pch_gpios(&mainboard_gpio_map); - ich7_enable_lpc(); + i82801gx_lpc_setup(); + mb_lpc_decode(); dlpc_init(); /* dock_init initializes the DLPC switch on |