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-rw-r--r--src/mainboard/lenovo/s230u/Kconfig74
-rw-r--r--src/mainboard/lenovo/s230u/Kconfig.name2
-rw-r--r--src/mainboard/lenovo/s230u/Makefile.inc15
-rw-r--r--src/mainboard/lenovo/s230u/acpi/ec.asl364
-rw-r--r--src/mainboard/lenovo/s230u/acpi/gpe.asl57
-rw-r--r--src/mainboard/lenovo/s230u/acpi/platform.asl50
-rw-r--r--src/mainboard/lenovo/s230u/acpi/superio.asl1
-rw-r--r--src/mainboard/lenovo/s230u/acpi_tables.c33
-rw-r--r--src/mainboard/lenovo/s230u/board_info.txt6
-rw-r--r--src/mainboard/lenovo/s230u/devicetree.cb138
-rw-r--r--src/mainboard/lenovo/s230u/dsdt.asl31
-rw-r--r--src/mainboard/lenovo/s230u/ec.c49
-rw-r--r--src/mainboard/lenovo/s230u/ec.h19
-rw-r--r--src/mainboard/lenovo/s230u/gpio.c254
-rw-r--r--src/mainboard/lenovo/s230u/hda_verb.c129
-rw-r--r--src/mainboard/lenovo/s230u/mainboard.c93
-rw-r--r--src/mainboard/lenovo/s230u/romstage.c127
-rw-r--r--src/mainboard/lenovo/s230u/smihandler.c140
-rw-r--r--src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex16
-rw-r--r--src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex16
-rw-r--r--src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex16
-rw-r--r--src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex16
-rw-r--r--src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex16
-rw-r--r--src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex16
-rw-r--r--src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex16
25 files changed, 1694 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig
new file mode 100644
index 0000000000..4b6727ca22
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/Kconfig
@@ -0,0 +1,74 @@
+if BOARD_LENOVO_S230U
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select USE_NATIVE_RAMINIT
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_COMPAL_ENE932
+ select EC_ACPI
+ select NO_UART_ON_SUPERIO
+ select BOARD_ROMSIZE_KB_12288
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select INTEL_INT15
+ select SANDYBRIDGE_IVYBRIDGE_LVDS
+ select SERIRQ_CONTINUOUS_MODE
+ select MAINBOARD_HAS_LPC_TPM
+ select GENERIC_SPD_BIN
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default lenovo/s230u
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ThinkPad S230U (Twist)"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config EC_BASE_ADDRESS
+ hex
+ default 0xff000000
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 1
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 60
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x17aa
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x2205
+
+endif # BOARD_LENOVO_S230U
diff --git a/src/mainboard/lenovo/s230u/Kconfig.name b/src/mainboard/lenovo/s230u/Kconfig.name
new file mode 100644
index 0000000000..61d1ab7f16
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LENOVO_S230U
+ bool "ThinkPad S230U (Twist)"
diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc
new file mode 100644
index 0000000000..226eca85b0
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/Makefile.inc
@@ -0,0 +1,15 @@
+romstage-y += gpio.c
+ramstage-y += ec.c
+smm-y += smihandler.c
+
+# FIXME: SPD images for samsung_8gb and hynix_8gb are missing.
+# It's possible that no mainboards with that variation were manufactured.
+SPD_SOURCES = elpida_4gb # 0b0000
+SPD_SOURCES += samsung_4gb # 0b0001
+SPD_SOURCES += hynix_4gb # 0b0010
+SPD_SOURCES += elpida_8gb # 0b0011
+SPD_SOURCES += elpida_8gb # 0b0100 FIXME: samsung_8gb
+SPD_SOURCES += elpida_8gb # 0b0101 FIXME: hynix_8gb
+SPD_SOURCES += elpida_2gb # 0b0110
+SPD_SOURCES += samsung_2gb # 0b0111
+SPD_SOURCES += hynix_2gb # 0b1000
diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl
new file mode 100644
index 0000000000..b59c269ebf
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/acpi/ec.asl
@@ -0,0 +1,364 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ * Copyright (c) 2013 Vladimir Serbinenko <phcoder@gmail.com>
+ * Copyright (c) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 0)
+
+ Name (_GPE, THINKPAD_EC_GPE)
+ Mutex (ECLK, 0x07)
+
+ /* EmbeddedControl should work as well, but memory mapped is faster. */
+ OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ Offset(0x00),
+ , 1,
+ , 1,
+ HKFA, 1, // FN lock (Hotkey / FN row toggle)
+ , 1,
+ , 1,
+ , 1,
+ , 1,
+
+ Offset(0x0c),
+ HLCL, 8, // LED control
+
+ Offset(0x46),
+ , 4,
+ ONAC, 1,
+ , 3,
+
+ Offset(0x81),
+ PAGE, 8,
+ }
+
+ /* Battery info page 0 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xA0),
+ SBRC, 16, /* Remaining capacity */
+ SBFC, 16, /* Full-charge capacity */
+ SBAE, 16,
+ SBRS, 16,
+ SBAC, 16, /* Present rate */
+ SBVO, 16, /* Present voltage */
+ SBAF, 16,
+ SBBS, 16,
+ }
+
+ /* Battery info page 1 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xA0),
+ , 15,
+ SBCM, 1, /* Power unit (0 == mA/mAh, 1 == mW/mWh) */
+ SBMD, 16,
+ SBCC, 16,
+ }
+
+ /* Battery info page 2 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xA0),
+ SBDC, 16, /* Design Capacity */
+ SBDV, 16, /* Design Voltage */
+ SBOM, 16,
+ SBSI, 16,
+ SBDT, 16,
+ SBSN, 16, /* Serial number */
+ }
+
+ /* Battery info page 4 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xA0),
+ SBCH, 32, /* Type (LiON) */
+ }
+
+ /* Battery info page 5 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xA0),
+ SBMN, 128, /* Manufacturer */
+ }
+
+ /* Battery info page 6 */
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0xA0),
+ SBDN, 128, /* Model */
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ IO (Decode16, 0x700, 0x700, 0, 8)
+ Memory32Fixed(ReadOnly, CONFIG_EC_BASE_ADDRESS, 0x1000, FF00)
+ })
+ Return (ECMD)
+ }
+
+ /* Increase brightness hotkey */
+ Method (_Q14, 0, NotSerialized) {
+ BRIGHTNESS_UP()
+ ^HKEY.MHKQ (0x1010)
+ }
+
+ /* Decrease brightness hotkey */
+ Method (_Q15, 0, NotSerialized) {
+ BRIGHTNESS_DOWN()
+ ^HKEY.MHKQ (0x1011)
+ }
+
+ /* Video output switch hotkey */
+ Method (_Q16, 0, NotSerialized) {
+ Notify (ACPI_VIDEO_DEVICE, 0x82)
+ ^HKEY.MHKQ (0x1007)
+ }
+
+ Method (_Q19, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x1018)
+ }
+
+ /* Switched to AC power */
+ Method (_Q26, 0, NotSerialized)
+ {
+ Store (One, PWRS)
+ Notify (^AC, 0x80)
+ Notify (^BAT0, 0x80)
+ \PNOT ()
+ ^HKEY.MHKQ (0x6040)
+ }
+
+ /* Switched to battery power */
+ Method (_Q27, 0, NotSerialized)
+ {
+ Store (Zero, PWRS)
+ Notify (^AC, 0x80)
+ Notify (^BAT0, 0x80)
+ \PNOT ()
+ ^HKEY.MHKQ (0x6040)
+ }
+
+ /* Lid openend */
+ Method (_Q2A, 0, NotSerialized)
+ {
+ Store (One, LIDS)
+ Notify(^LID, 0x80)
+ ^HKEY.MHKQ (0x5002)
+ }
+
+ /* Lid closed */
+ Method (_Q2B, 0, NotSerialized)
+ {
+ Store (Zero, LIDS)
+ Notify(^LID, 0x80)
+ ^HKEY.MHKQ (0x5001)
+ }
+
+ /* Tablet swivel down */
+ Method (_Q35, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x60c0)
+ ^HKEY.MHKQ (0x500a)
+ }
+
+ /* Tablet swivel up */
+ Method (_Q36, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x60c0)
+ ^HKEY.MHKQ (0x5009)
+ }
+
+ /* Tablet rotate lock button */
+ Method (_Q37, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x6020)
+ }
+
+ /* Numlock pressed */
+ Method (_Q3F, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x6000)
+ }
+
+ /* RFKill status changed */
+ Method (_Q41, 0, NotSerialized) {
+ ^HKEY.MHKQ (0x7000)
+ }
+
+ /* Mute hotkey */
+ Method (_Q43, 0, NotSerialized) {
+ ^HKEY.MHKQ (0x1017)
+ }
+
+ /* Settings hotkey */
+ Method (_Q5A, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x101D)
+ }
+
+ /* Search hotkey */
+ Method (_Q5B, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x101E)
+ }
+
+ /* Scale hotkey */
+ Method (_Q5C, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x101F)
+ }
+
+ /* File hotkey */
+ Method (_Q5D, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x1020)
+ }
+
+ /* RFkill hotkey */
+ Method (_Q64, 0, NotSerialized) {
+ ^HKEY.MHKQ (0x1005)
+ }
+
+ /* Mic mute hotkey */
+ Method (_Q6A, 0, NotSerialized)
+ {
+ ^HKEY.MHKQ (0x101B)
+ }
+
+ /* FN key pressed */
+ Method (_Q70, 0, NotSerialized) { }
+
+ /* FN+Esc pressed / FN row mode switch */
+ Method (_Q74, 0, NotSerialized) {
+ XOr(One, HKFA, HKFA)
+ ^HKEY.MHKQ (0x6060)
+ }
+
+ /* Implements enough of the Lenovo hotkey device for
+ * thinkpad-acpi to work, no real support for hotkey masking */
+ Device (HKEY)
+ {
+ Name (_HID, EisaId ("LEN0068"))
+
+ Name (DHKC, Zero)
+ Name (DHKV, Zero)
+ Name (DHKN, 0xFC018070) // Hotkey mask
+ Mutex (XDHK, 0x07)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (MHKV, 0, NotSerialized)
+ {
+ Return (0x0100) // Interface version 1.0
+ }
+
+ Method (MHKA, 0, NotSerialized) // Hotkey all mask
+ {
+ Return (0xFFFFFFFF)
+ }
+
+ Method (MHKM, 2, NotSerialized) // Set hotkey mask
+ {
+ Acquire (XDHK, 0xFFFF)
+
+ ShiftLeft (One, Decrement (Arg0), Local0)
+ If (Arg1) {
+ Or (Local0, DHKN, DHKN)
+ } Else {
+ And (Not(Local0), DHKN, DHKN)
+ }
+
+ Release (XDHK)
+ }
+
+ Method (MHKC, 1, NotSerialized) // Hotkey disable?
+ {
+ Acquire (XDHK, 0xFFFF)
+
+ Store (Arg0, DHKC)
+
+ Release (XDHK)
+ }
+
+ Method (MHKP, 0, NotSerialized) // Hotkey poll
+ {
+ Acquire (XDHK, 0xFFFF)
+
+ Store (Zero, Local0)
+
+ if (DHKV) {
+ Store (DHKV, Local0)
+ Store (Zero, DHKV)
+ }
+
+ Release (XDHK)
+
+ Return (Local0)
+ }
+
+ Method (MHKQ, 1, NotSerialized) // Send hotkey event
+ {
+ Acquire (XDHK, 0xFFFF)
+
+ Store (Arg0, DHKV)
+
+ Release (XDHK)
+
+ Notify (HKEY, 0x80) // Status Change
+ }
+ }
+
+ /* LED support for thinkpad-acpi */
+ Method (LED, 2, NotSerialized)
+ {
+ Or (Arg0, Arg1, HLCL)
+ }
+
+ Device (AC)
+ {
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package (1) { \_SB })
+
+ Method (_PSR, 0, NotSerialized)
+ {
+ Return (ONAC)
+ }
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ }
+
+ /* Battery is H8 compatible, but requires an explicit delay */
+ #define BATTERY_PAGE_DELAY_MS 20
+ #include <ec/lenovo/h8/acpi/battery.asl>
+
+ /* LID is H8 compatible */
+ #include <ec/lenovo/h8/acpi/lid.asl>
+}
diff --git a/src/mainboard/lenovo/s230u/acpi/gpe.asl b/src/mainboard/lenovo/s230u/acpi/gpe.asl
new file mode 100644
index 0000000000..a69f5629b1
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/acpi/gpe.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (_GPE)
+{
+ Field(GPIO, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x2c), // GPIO Invert
+ , 2,
+ GV02, 1,
+ , 1,
+ GV04, 1,
+ }
+
+ Name (PDET, Zero)
+ Method (PNOT, 2, Serialized) {
+ ShiftLeft (Arg0, Arg1, Local0)
+ Not( ShiftLeft (One, Arg1), Local1)
+ Or (Local0, And (Local1, PDET), PDET)
+ If (LEqual (PDET, Zero)) {
+ // Palm removed
+ \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B1)
+ } Else {
+ // Palm detected
+ \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B0)
+ }
+ }
+
+ /* Palm detect sensor 1 */
+ Method (_L12, 0, NotSerialized) {
+ // Invert trigger
+ Store(GP02, GV02)
+
+ PNOT (GP02, 0)
+ }
+
+ /* Palm detect sensor 2 */
+ Method (_L14, 0, NotSerialized) {
+ // Invert trigger
+ Store(GP04, GV04)
+
+ PNOT (GP04, 1)
+ }
+}
diff --git a/src/mainboard/lenovo/s230u/acpi/platform.asl b/src/mainboard/lenovo/s230u/acpi/platform.asl
new file mode 100644
index 0000000000..d90715ab51
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/acpi/platform.asl
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ /* Turn on radios */
+ Store (One, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */
+ Store (One, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */
+ /* There also is RF_OFF# on pin 20, controlled by the EC */
+
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* Turn off radios */
+ Store (Zero, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */
+ Store (Zero, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */
+ /* There also is RF_OFF# on pin 20, controlled by the EC */
+}
+
+Scope(\_SI)
+{
+ Method(_SST, 1, NotSerialized)
+ {
+ If (LLess(Arg0, 2))
+ {
+ /* Thinkpad LED on */
+ \_SB.PCI0.LPCB.EC0.LED (Zero, 0x80)
+ }
+ Else
+ {
+ /* Thinkpad LED blinking */
+ \_SB.PCI0.LPCB.EC0.LED (Zero, 0xC0)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/s230u/acpi/superio.asl b/src/mainboard/lenovo/s230u/acpi/superio.asl
new file mode 100644
index 0000000000..f2b35ba9c1
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c
new file mode 100644
index 0000000000..21fce85f5a
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/acpi_tables.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* The LID is open by default */
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/lenovo/s230u/board_info.txt b/src/mainboard/lenovo/s230u/board_info.txt
new file mode 100644
index 0000000000..09ddde1f85
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2012
diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb
new file mode 100644
index 0000000000..ff4c6c4cff
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/devicetree.cb
@@ -0,0 +1,138 @@
+chip northbridge/intel/sandybridge
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00000060"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "2000"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "500"
+ register "gpu_panel_power_up_delay" = "600"
+ register "gpu_pch_backlight" = "0x041e041e"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 01.0 off # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x17aa 0x2205
+ end
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x00000000"
+ register "gen2_dec" = "0x000c0701"
+ register "gen3_dec" = "0x000c0069"
+ register "gen4_dec" = "0x000c06a1"
+ register "gpi13_routing" = "2"
+ register "gpi7_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x11"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 16.0 off # Management Engine Interface 1
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 on # PCIe Port #4
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x17aa 0x2205
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x17aa 0x2205
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x17aa 0x2205
+ chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
+ device i2c 54 on
+ end
+ device i2c 55 on
+ end
+ device i2c 56 on
+ end
+ device i2c 57 on
+ end
+ device i2c 5c on
+ end
+ device i2c 5d on
+ end
+ device i2c 5e on
+ end
+ device i2c 5f on
+ end
+ end
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl
new file mode 100644
index 0000000000..6cf26fd20f
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/dsdt.asl
@@ -0,0 +1,31 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+#define EC_LENOVO_H8_ME_WORKAROUND 1
+#define THINKPAD_EC_GPE 23
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ #include "acpi/platform.asl"
+ #include "acpi/gpe.asl"
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/s230u/ec.c b/src/mainboard/lenovo/s230u/ec.c
new file mode 100644
index 0000000000..f3e01b68be
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/ec.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "ec.h"
+#include <ec/compal/ene932/ec.h>
+
+/* The keyboard matrix tells the EC how the keyboard is wired internally */
+static void set_keyboard_matrix_us(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE5);
+}
+
+/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
+static void enter_apm_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE9);
+}
+
+void lenovo_s230u_ec_init(void)
+{
+ set_keyboard_matrix_us();
+
+ /*
+ * The EC has a special "blinking Caps Lock LED" mode which it normally
+ * enters when it believes the OS is not responding. It occasionally
+ * disables battery charging when in this mode, although other
+ * functionality is unaffected. Although the EC starts in APM mode by
+ * default, it only leaves the "blinking Caps Lock LED" mode after
+ * receiving the following command.
+ */
+ enter_apm_mode();
+
+ /* Enable external USB port power. */
+ ec_mm_set_bit(0x3b, 4);
+}
diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h
new file mode 100644
index 0000000000..afb6cdc8fb
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/ec.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#ifndef _MAINBOARD_LENOVO_S230U_EC_H
+#define _MAINBOARD_LENOVO_S230U_EC_H
+
+#ifndef __SMM__
+void lenovo_s230u_ec_init(void);
+#endif
+
+#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x)))
+#define ec_mm_read(addr) (ECMM(0x100 + addr))
+#define ec_mm_write(addr, data) (ECMM(0x100 + addr) = data)
+#define ec_mm_set_bit(addr, bit) (ECMM(0x100 + addr) |= 1 << bit)
+#define ec_mm_clr_bit(addr, bit) (ECMM(0x100 + addr) &= ~(1 << bit))
+
+#endif /* _MAINBOARD_LENOVO_S230U_EC_H */
diff --git a/src/mainboard/lenovo/s230u/gpio.c b/src/mainboard/lenovo/s230u/gpio.c
new file mode 100644
index 0000000000..a0e30c26e7
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/gpio.c
@@ -0,0 +1,254 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO, /* POUT1# (from palm sensor 1) */
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO, /* POUT2# (from palm sensor 2) */
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO, /* PA0_WAKEUP (To sensor hub PA0) */
+ .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# (from EC) */
+ .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# (from EC) */
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# */
+ .gpio16 = GPIO_MODE_GPIO, /* RAM_ID2 */
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO, /* mSATA_DET# (from WWAN/mSATA mPCIe pin 51) */
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_OUTPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_OUTPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_OUTPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio11 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_OUTPUT,
+ .gpio14 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_HIGH,
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio3 = GPIO_LEVEL_HIGH,
+ .gpio5 = GPIO_LEVEL_HIGH,
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio11 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio13 = GPIO_LEVEL_HIGH,
+ .gpio14 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_HIGH,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_HIGH,
+ .gpio29 = GPIO_LEVEL_LOW,
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio2 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio6 = GPIO_NO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+ .gpio16 = GPIO_NO_INVERT,
+ .gpio17 = GPIO_NO_INVERT,
+ .gpio27 = GPIO_NO_INVERT,
+ .gpio31 = GPIO_NO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio33 = GPIO_MODE_GPIO, /* PCH_WLBT_OFF_5# (to WLAN mPCIe pin 5) */
+ /* GPIO34 marked as PCH_BT_ON#, but is native (STP_PCI#) */
+ .gpio35 = GPIO_MODE_GPIO, /* 3G_DET# (from WWAN/mSATA mPCIe pin 43) */
+ .gpio36 = GPIO_MODE_GPIO, /* PCH_WLBT_OFF_51# (to WLAN mPCIe pin 51) */
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO, /* 3G_OFF# (to WWAN/mSATA mPCIe pin 20) */
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO, /* RAM_ID3 */
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ /* GPIO55 marekd as WL_OFF#, but is native (GNT3#) */
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_OUTPUT,
+ .gpio41 = GPIO_DIR_OUTPUT,
+ .gpio42 = GPIO_DIR_OUTPUT,
+ .gpio43 = GPIO_DIR_OUTPUT,
+ .gpio44 = GPIO_DIR_OUTPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_LOW,
+ .gpio41 = GPIO_LEVEL_HIGH,
+ .gpio42 = GPIO_LEVEL_HIGH,
+ .gpio43 = GPIO_LEVEL_HIGH,
+ .gpio44 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_HIGH,
+ .gpio46 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio50 = GPIO_LEVEL_LOW,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO, /* RAM_ID1 */
+ .gpio71 = GPIO_MODE_GPIO, /* RAM_ID0 */
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio74 = GPIO_MODE_GPIO,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_OUTPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_OUTPUT,
+ .gpio74 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_HIGH,
+ .gpio65 = GPIO_LEVEL_HIGH,
+ .gpio68 = GPIO_LEVEL_LOW,
+ .gpio72 = GPIO_LEVEL_HIGH,
+ .gpio74 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c
new file mode 100644
index 0000000000..f2da2c4756
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/hda_verb.c
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2017 Tobias Diedrich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC
+ 0x17aa21fa, // Subsystem ID
+ 0x0000000c, // Number of 4 dword sets
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01 - NodeInfo */
+ AZALIA_SUBVENDOR(0x0, 0x17AA21FA),
+
+ /*
+ * PIN_CFG:
+ * 31:30 Port connectivity
+ * 00 Connected to jack
+ * 01 No physical connection
+ * 10 Fixed function (integrated speaker/mic)
+ * 11 Jack + internal
+ * 29:24 Location
+ * See HDA spec for full matrix
+ * 23:20 Default device
+ * 0 Line out 4 S/PDIF out 8 Line in c S/PDIF in
+ * 1 Speaker 5 Digital out 9 Aux d Digital in
+ * 2 HP out 6 Modem line a Mic in e Reserved
+ * 3 CD 7 Modem handse b Telephony f Other
+ * 19:16 Connection type
+ * 0 Unknown 4 RCA 8 Multichannel analog DIN
+ * 1 1/8" jack 5 Optical 9 XLR
+ * 2 1/4" jack 6 Digital a RJ-11
+ * 3 ATAPI 7 Analog b Combination f Other
+ * 15:12 Color
+ * 0 Unknown 4 Green 8 Purple
+ * 1 Black 5 Red 9 Pink
+ * 2 Grey 6 Orange a-d Reserved
+ * 3 Blue 7 Yellow e White f Other
+ * 11:8 Misc
+ * bit0 Jack detect override 1-3 Reserved
+ * 7:4 Default association
+ * 0 Reserved/Not initialized
+ * f Lowest priority
+ * 3:0 Sequence
+ * For stream channel to in/out mapping
+ */
+
+ /*
+ * NID 0x12 - Digital MIC
+ * Fixed function, mic in, digital
+ */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60940),
+ /*
+ * NID 0x14 - SPK out
+ * Fixed function, speaker, analog
+ */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+ /*
+ * NID 0x15 - HP out
+ * Location left, headphone out, 1/8" jack, black
+ */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
+ /* NID 0x17 - ? (Unconnected) */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+ /*
+ * NID 0x18 - MIC1 in
+ * Location left, mic in, 1/8" jack, black
+ */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830),
+ /* NID 0x19 - MIC2 in (Unconnected) */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+ /* NID 0x1a - Line1 in (Unconnected) */
+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+ /* NID 0x1b - Line2 in (Unconnected) */
+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+ /* NID 0x1d - PCBEEP */
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40148605),
+ /* NID 0x1e - S/PDIF out (Unconnected) */
+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+
+ 0x01470740, // Enable output for NID 0x14 (Speaker out)
+ 0x015707C0, // Enable output & HP amp for NID 0x15 (HP out)
+ 0x01870724, // Enable Vrefout NID 0x18 (MIC1 in)
+ 0x00170500, // Set power state to D0
+
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of IDs
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030)
+};
+
+const u32 pc_beep_verbs[] = {
+ /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+ 0x02177a00,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c
new file mode 100644
index 0000000000..9ed2a4b14f
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/mainboard.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <ec/acpi/ec.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+#include <string.h>
+#include <smbios.h>
+#include "ec.h"
+
+#include <arch/acpi.h>
+
+static void mainboard_init(device_t dev)
+{
+ RCBA32(0x38c8) = 0x00002005;
+ RCBA32(0x38c4) = 0x00802005;
+ RCBA32(0x38c0) = 0x00000007;
+}
+
+static u8 mainboard_fill_ec_version(char *buf, u8 buf_len)
+{
+ u8 i, c;
+ char str[16 + 1]; /* 16 ASCII chars + \0 */
+
+ /* Build ID */
+ for (i = 0; i < 8; i++) {
+ c = ec_mm_read(0xf0 + i);
+ if (c < 0x20 || c > 0x7f) {
+ i = snprintf(str, sizeof(str), "*INVALID");
+ break;
+ }
+ str[i] = c;
+ }
+
+ i = MIN(buf_len, i);
+ memcpy(buf, str, i);
+
+ return i;
+}
+
+static void mainboard_smbios_strings(
+ struct device *dev, struct smbios_type11 *t)
+{
+ char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-";
+ u16 fwvh, fwvl;
+
+ mainboard_fill_ec_version(tpec + 35, 17);
+ t->count = smbios_add_string(t->eos, tpec);
+
+ /* Apparently byteswapped compared to H8 */
+ fwvh = ec_mm_read(0xe8);
+ fwvl = ec_mm_read(0xe9);
+
+ printk(BIOS_INFO, "EC Firmware ID %.54s, Version %d.%d%d%c\n", tpec,
+ fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf));
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->get_smbios_strings = mainboard_smbios_strings,
+
+ install_intel_vga_int15_handler(
+ GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT,
+ 0);
+
+ if (!acpi_is_wakeup_s3())
+ lenovo_s230u_ec_init();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
new file mode 100644
index 0000000000..ce751653c2
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cbfs.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <southbridge/intel/common/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include "ec.h"
+
+#define SPD_LEN 256
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
+
+ /* Memory map KB9012 EC registers */
+ pci_write_config32(
+ PCI_DEV(0, 0x1f, 0), 0x98,
+ CONFIG_EC_BASE_ADDRESS | 1);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0);
+
+ #ifdef CONFIG_USBDEBUG
+ /* Enable external USB port power. */
+ ec_mm_set_bit(0x3b, 4);
+ #endif
+}
+
+void rcba_config(void)
+{
+ /* Disable devices. */
+ RCBA32(0x3414) = 0x00000020;
+ RCBA32(0x3418) = 0x17f41fe3;
+
+}
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 0, 1 },
+ { 1, 1, 2 },
+ { 1, 0, 2 },
+ { 0, 0, 3 },
+ { 0, 1, 3 },
+ { 1, 0, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+static const char *mainboard_spd_names[9] = {
+ "ELPIDA 4GB",
+ "SAMSUNG 4GB",
+ "HYNIX 4GB",
+ "ELPIDA 8GB",
+ "SAMSUNG 8GB",
+ "HYNIX 8GB",
+ "ELPIDA 2GB",
+ "SAMSUNG 2GB",
+ "HYNIX 2GB",
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ void *spd_file;
+ size_t spd_file_len = 0;
+ const int spd_gpios[] = {71, 70, 16, 48, -1};
+
+ u32 spd_index = get_gpios(spd_gpios);
+ if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) {
+ /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
+ spd_index = 6;
+ }
+
+ printk(BIOS_INFO, "SPD index %d (%s)\n",
+ spd_index, mainboard_spd_names[spd_index]);
+
+ /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+
+ if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN)
+ die("SPD data not found.");
+
+ memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN);
+}
diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c
new file mode 100644
index 0000000000..755f176e91
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/smihandler.c
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "ec.h"
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <delay.h>
+#include <ec/acpi/ec.h>
+#include <ec/compal/ene932/ec.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#define GPE_PALMDET1 2
+#define GPE_PALMDET2 4
+#define GPE_EC_SCI 7
+#define GPE_EC_SMI 8
+/* FIXME: check this */
+#define GPE_EC_WAKE 13
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ return 0;
+}
+
+enum sleep_states {
+ S0 = 0,
+ S1 = 1,
+ S3 = 3,
+ S4 = 4,
+ S5 = 5,
+};
+
+enum ec_smi_event {
+ EC_SMI_EVENT_IDLE = 0x80,
+ EC_SMI_BATTERY_LOW = 0xb3,
+};
+
+/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs. */
+static void ec_enter_apm_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE9);
+}
+/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs. */
+static void ec_enter_acpi_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE8);
+}
+
+static uint8_t ec_get_smi_event(void)
+{
+ ec_kbc_write_cmd(0x56);
+ return ec_kbc_read_ob();
+}
+
+static void ec_process_smi(uint8_t src)
+{
+ /*
+ * Reading the SMI source satisfies the EC in terms of responding to
+ * the event, regardless of whether we take an action or not.
+ */
+
+ printk(BIOS_DEBUG, "Unhandled EC_SMI event 0x%x\n", src);
+}
+
+static void handle_ec_smi(void)
+{
+ uint8_t src;
+
+ while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE)
+ ec_process_smi(src);
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << GPE_EC_SMI))
+ handle_ec_smi();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data);
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ printk(BIOS_DEBUG, "Enable ACPI mode\n");
+ ec_enter_acpi_mode();
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
+ gpi_route_interrupt(GPE_PALMDET1, GPI_IS_SCI);
+ gpi_route_interrupt(GPE_PALMDET2, GPI_IS_SCI);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ printk(BIOS_DEBUG, "Disable ACPI mode\n");
+ ec_enter_apm_mode();
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data);
+ }
+ return 0;
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (slp_typ == S3) {
+ u8 ec_wake = ec_read(0x32);
+ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */
+ if (ec_wake & 0x14)
+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
+ }
+}
diff --git a/src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex b/src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex
new file mode 100644
index 0000000000..c6e0477ff1
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex
@@ -0,0 +1,16 @@
+92 10 0b 03 03 11 03 0a 03 52 01 08 0c 00 7c 00
+69 78 69 3c 69 11 20 89 00 05 3c 3c 01 68 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 fe 00 00 00 00 00 00 00 f0 61
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 02 fe 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex b/src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex
new file mode 100644
index 0000000000..b15d051707
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex
@@ -0,0 +1,16 @@
+92 10 0b 03 04 19 02 0a 03 52 01 08 0c 00 7e 00
+69 78 69 30 69 11 20 89 20 08 3c 3c 00 f0 83 81
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 fe 00 00 00 00 00 00 00 b1 81
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex b/src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex
new file mode 100644
index 0000000000..067ff640c7
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex
@@ -0,0 +1,16 @@
+92 10 0b 03 04 21 02 09 03 52 01 08 0c 00 7e 00
+69 78 69 30 69 11 20 89 20 08 3c 3c 00 f0 83 81
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex b/src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex
new file mode 100644
index 0000000000..0f01da51d2
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex
@@ -0,0 +1,16 @@
+92 11 0b 03 03 11 00 0a 03 52 01 08 0c 00 7e 00
+69 78 69 3c 69 11 20 89 00 05 3c 3c 01 68 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex b/src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex
new file mode 100644
index 0000000000..9b39b751f4
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex
@@ -0,0 +1,16 @@
+92 11 0b 03 04 19 02 0a 03 52 01 08 0c 00 7e 00
+69 78 69 3c 69 11 20 89 20 08 3c 3c 01 68 83 05
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex b/src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex
new file mode 100644
index 0000000000..bc8810f21f
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex
@@ -0,0 +1,16 @@
+92 11 0b 03 03 11 02 0a 03 11 01 08 0c 00 3e 00
+69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 01
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex b/src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex
new file mode 100644
index 0000000000..d75d0692c4
--- /dev/null
+++ b/src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex
@@ -0,0 +1,16 @@
+92 11 0b 03 04 19 02 0a 03 11 01 08 0c 00 3e 00
+69 78 69 30 69 11 20 89 20 08 3c 3c 00 f0 83 01
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 00:12:48 +0000