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-rw-r--r--src/mainboard/lenovo/x220/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/x220/gpio.c (renamed from src/mainboard/lenovo/x220/gpio.h)2
-rw-r--r--src/mainboard/lenovo/x220/romstage.c103
3 files changed, 22 insertions, 84 deletions
diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc
index d514d4b9f9..265059ae9f 100644
--- a/src/mainboard/lenovo/x220/Makefile.inc
+++ b/src/mainboard/lenovo/x220/Makefile.inc
@@ -18,3 +18,4 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c
diff --git a/src/mainboard/lenovo/x220/gpio.h b/src/mainboard/lenovo/x220/gpio.c
index 59e00c91f7..83a0db30db 100644
--- a/src/mainboard/lenovo/x220/gpio.h
+++ b/src/mainboard/lenovo/x220/gpio.c
@@ -359,7 +359,7 @@ static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_HIGH,
};
-static const struct pch_gpio_map x220_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index a516ee617c..ba48fac574 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -35,11 +35,9 @@
#include "southbridge/intel/bd82x6x/pch.h"
#include "southbridge/intel/bd82x6x/gpio.h"
#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
-#include "gpio.h"
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
/* X230 EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
@@ -57,7 +55,7 @@ static void pch_enable_lpc(void)
0x80010000);
}
-static void rcba_config(void)
+void rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
@@ -106,85 +104,24 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
-{
- int s3resume = 0;
- spd_raw_data spd[4];
-
- if (MCHBAR16(SSKPD) == 0xCAFE) {
- outb(0x6, 0xcf9);
- hlt ();
- }
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&x220_gpio_map);
-
- early_usb_init((struct southbridge_usb_port []) {
- { 1, 0, 0 },
- { 1, 1, 1 },
- { 1, 1, 3 },
- { 1, 1, 3 },
- { 1, 1, -1 },
- { 1, 1, -1 },
- { 1, 0, 2 },
- { 1, 0, 2 },
- { 1, 1, 6 },
- { 1, 1, 5 },
- { 1, 1, 6 },
- { 1, 1, 6 },
- { 1, 1, 7 },
- { 1, 1, 6 },
- });
-
- /* Initialize console device(s) */
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Perform some early chipset initialization required
- * before RAM initialization can work
- */
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
- printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
-
- s3resume = southbridge_detect_s3_resume();
-
- post_code(0x38);
- /* Enable SPD ROMs and DDR-III DRAM */
- enable_smbus();
-
- post_code(0x39);
-
- post_code(0x3a);
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- memset (spd, 0, sizeof (spd));
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, -1 },
+ { 1, 1, -1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 1, 6 },
+ { 1, 1, 5 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
read_spd (&spd[0], 0x50);
read_spd (&spd[2], 0x51);
-
- init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
-
- timestamp_add_now(TS_AFTER_INITRAM);
- post_code(0x3c);
-
- rcba_config();
- post_code(0x3d);
-
- northbridge_romstage_finalize(s3resume);
-
- post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
}