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Diffstat (limited to 'src/mainboard/lenovo/g505s')
-rw-r--r--src/mainboard/lenovo/g505s/OemCustomize.c43
1 files changed, 35 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c
index aaed339e96..7e4fa6e82f 100644
--- a/src/mainboard/lenovo/g505s/OemCustomize.c
+++ b/src/mainboard/lenovo/g505s/OemCustomize.c
@@ -70,48 +70,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23),
- PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
},
};
@@ -132,7 +160,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
- /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
},
};