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-rw-r--r--src/mainboard/kontron/986lcd-m/Config.lb13
-rw-r--r--src/mainboard/kontron/986lcd-m/Options.lb2
-rw-r--r--src/mainboard/kontron/986lcd-m/auto.c7
3 files changed, 19 insertions, 3 deletions
diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb
index 9f965e29af..833478bb79 100644
--- a/src/mainboard/kontron/986lcd-m/Config.lb
+++ b/src/mainboard/kontron/986lcd-m/Config.lb
@@ -82,7 +82,7 @@ if HAVE_ACPI_TABLES
object acpi_tables.o
makerule dsdt.c
depends "$(MAINBOARD)/dsdt.dsl"
- action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl"
+ action "iasl -p dsdt -tc $(MAINBOARD)/dsdt.dsl"
action "mv $(PWD)/dsdt.hex dsdt.c"
end
object ./dsdt.o
@@ -187,9 +187,18 @@ chip northbridge/intel/i945
device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x05"
+ register "pirqb_routing" = "0x07"
+ register "pirqc_routing" = "0x06"
+ register "pirqd_routing" = "0x07"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x05"
+
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
device pci 1b.0 on end # High Definition Audio
diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb
index 926e69820b..dbf21d5801 100644
--- a/src/mainboard/kontron/986lcd-m/Options.lb
+++ b/src/mainboard/kontron/986lcd-m/Options.lb
@@ -233,7 +233,7 @@ default FALLBACK_SIZE=131072
##
## coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default _RAMBASE=0x00100000
##
## Load the payload from the ROM
diff --git a/src/mainboard/kontron/986lcd-m/auto.c b/src/mainboard/kontron/986lcd-m/auto.c
index c708f1ae15..5a6d88a850 100644
--- a/src/mainboard/kontron/986lcd-m/auto.c
+++ b/src/mainboard/kontron/986lcd-m/auto.c
@@ -169,6 +169,13 @@ static void early_superio_config_w83627thg(void)
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
+ /* Enable HWM */
+ dev=PNP_DEV(0x2e, W83627THG_HWM);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
+ pnp_set_enable(dev, 1);
+
pnp_exit_ext_func_mode(dev);
dev=PNP_DEV(0x4e, W83627THG_SP1);