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-rw-r--r--src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl87
-rw-r--r--src/mainboard/kontron/ktqm77/acpi_tables.c18
-rw-r--r--src/mainboard/kontron/ktqm77/devicetree.cb9
-rw-r--r--src/mainboard/kontron/ktqm77/romstage.c58
4 files changed, 1 insertions, 171 deletions
diff --git a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index ceb40be356..0000000000
--- a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 secunet Security Networks AG
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Ivybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // LPC devices 0:1f.x
- // D31IP_TTIP THRT INTC -> PIRQC
- Package() { 0x001fffff, 2, 0, 18 },// D31IP_SMIP SMBUS INTC -> PIRQC
- Package() { 0x001fffff, 1, 0, 19 },// D31IP_SIP SATA INTB -> PIRQD (MSI)
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, 0, 23 },// D29IP_E1P EHCI1 INTA -> PIRQH
- // PCIe Root Ports 0:1c.x
- // D28IP_P8IP Slot? INTD -> PIRQD
- Package() { 0x001cffff, 3, 0, 19 },// D28IP_P4IP ETH2 INTD -> PIRQD (MSI)
- // D28IP_P7IP PCIEx1 INTC -> PIRQC
- Package() { 0x001cffff, 2, 0, 18 },// D28IP_P3IP ETH1 INTC -> PIRQC (MSI)
- // D28IP_P6IP 1394 INTB -> PIRQB (MSI)
- Package() { 0x001cffff, 1, 0, 17 },// D28IP_P2IP Slot? INTB -> PIRQB
- // D28IP_P5IP GbEPHY INTA -> PIRQA
- Package() { 0x001cffff, 0, 0, 16 },// D28IP_P1IP Slot? INTA -> PIRQA
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },// D27IP_ZIP HDA INTA -> PIRQG (MSI)
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, 0, 16 },// D26IP_E2P EHCI2 INTA -> PIRQA
- // ETH0 0:19.0
- Package() { 0x0019ffff, 0, 0, 20 },// D25IP_LIP ETH0 INTA -> PIRQE (MSI)
- // xHCI 0:14.0
- Package() { 0x0014ffff, 0, 0, 16 },// D20IP_XHCIIP xHCI INTA -> PIRQA (MSI)
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
- // PCIe PEG x16 0:1.0
- Package() { 0x0001ffff, 3, 0, 19 },// PEGx16 INTD -> PIRQD
- Package() { 0x0001ffff, 2, 0, 18 },// PEGx16 INTC -> PIRQC
- Package() { 0x0001ffff, 1, 0, 17 },// PEGx16 INTB -> PIRQB
- Package() { 0x0001ffff, 0, 0, 16 },// PEGx16 INTA -> PIRQA
- })
- } Else {
- Return (Package() {
- // LPC devices 0:1f.x
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- // EHCI #1 0:1d.0
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // EHCI #2 0:1a.0
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // ETH0 0:19.0
- Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
- // xHCI 0:14.0
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe PEG x16 0:1.0
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- })
- }
-}
diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c
index 0d90403bf0..d2d70e9fca 100644
--- a/src/mainboard/kontron/ktqm77/acpi_tables.c
+++ b/src/mainboard/kontron/ktqm77/acpi_tables.c
@@ -63,24 +63,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
acpi_update_thermal_table(gnvs);
}
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Local APICs */
- current = acpi_create_madt_lapics(current);
-
- /* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
-
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index fb180577a9..855fd5c7f6 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -27,15 +27,6 @@ chip northbridge/intel/sandybridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8b"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x8b"
- register "pirqf_routing" = "0x8b"
- register "pirqg_routing" = "0x8b"
- register "pirqh_routing" = "0x8b"
-
# Enable all SATA ports 0-5
register "sata_port_map" = "0x3f"
# Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 401314cd8d..bfe7715826 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -59,63 +59,7 @@ static void rcba_config(void)
{
u32 reg32;
- /*
- * D31IP_TTIP THRT INTC -> PIRQC
- * D31IP_SIP2 SATA2 NOINT
- * D31IP_SMIP SMBUS INTC -> PIRQC
- * D31IP_SIP SATA INTB -> PIRQD (MSI)
- * D29IP_E1P EHCI1 INTA -> PIRQH
- * D28IP_P8IP Slot? INTD -> PIRQD
- * D28IP_P7IP PCIEx1 INTC -> PIRQC
- * D28IP_P6IP 1394 INTB -> PIRQB (MSI)
- * D28IP_P5IP GbEPHY INTA -> PIRQA
- * D28IP_P4IP ETH2 INTD -> PIRQD (MSI)
- * D28IP_P3IP ETH1 INTC -> PIRQC (MSI)
- * D28IP_P2IP Slot? INTB -> PIRQB
- * D28IP_P1IP Slot? INTA -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- * D26IP_E2P EHCI2 INTA -> PIRQA
- * D25IP_LIP ETH0 INTA -> PIRQE (MSI)
- * D22IP_KTIP MEI NOINT
- * D22IP_IDERIP MEI NOINT
- * D22IP_MEI2IP MEI NOINT
- * D22IP_MEI1IP MEI NOINT
- * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI)
- * GFX INTA -> PIRQA (MSI)
- * PEGx16 INTA -> PIRQA
- * INTB -> PIRQB
- * INTC -> PIRQC
- * INTD -> PIRQD
- */
-
- /* Device interrupt pin register (board specific) */
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTC << D31IP_SMIP) | (INTB << D31IP_SIP);
- RCBA32(D29IP) = (INTA << D29IP_E1P);
- RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
- (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) |
- (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) |
- (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP);
- RCBA32(D27IP) = (INTA << D27IP_ZIP);
- RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (INTA << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
- RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
-
- /* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA);
- DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC);
- DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD);
- DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH);
- DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB);
- DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
- /* Enable IOAPIC (generic) */
- RCBA16(OIC) = 0x0100;
- /* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(OIC);
+ southbridge_configure_default_intmap();
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-19 11:23:30 +0000