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-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c7
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/mainboard.c11
2 files changed, 8 insertions, 10 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 86999fbab4..c2227ae935 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -17,6 +17,7 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <vendorcode/amd/cimx/sb800/SB800.h>
#include <stdint.h>
#include <stdlib.h>
@@ -63,11 +64,9 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
/* Get SB800 MMIO Base (AcpiMmioAddr) */
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (uint32_t)Data16 << 16;
Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index 0a12c3f66a..cbf75a49ce 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -128,12 +128,11 @@ static void mainboard_enable(struct device *dev)
/* enable GPP CLK0 thru CLK3 (interleaved) */
/* disable GPP CLK4 thru SLT_GFX_CLK */
- u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
- write8(misc_mem_clk_cntrl + 0, 0xFF);
- write8(misc_mem_clk_cntrl + 1, 0xFF);
- write8(misc_mem_clk_cntrl + 2, 0x00);
- write8(misc_mem_clk_cntrl + 3, 0x00);
- write8(misc_mem_clk_cntrl + 4, 0x00);
+ misc_write8(0, 0xff);
+ misc_write8(1, 0xff);
+ misc_write8(2, 0);
+ misc_write8(3, 0);
+ misc_write8(4, 0);
/*
* Initialize ASF registers to an arbitrary address because someone