diff options
Diffstat (limited to 'src/mainboard/jetway')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/jetway/pa78vm5/romstage.c | 10 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 4b2f711fc5..7f9171405d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -92,8 +92,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 044d0d8b0f..5121605004 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -114,10 +114,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); |