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-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl2
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/dsdt.asl2
2 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
index b666a4f350..702cb92032 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
@@ -23,8 +23,6 @@ Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
-Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
index 7e26bab43c..b5d60d4a92 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
@@ -47,7 +47,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
/* Contains the supported sleep states for this chipset */
- #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"