diff options
Diffstat (limited to 'src/mainboard/iwill')
| -rw-r--r-- | src/mainboard/iwill/dk8_htx/Config.lb | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/src/mainboard/iwill/dk8_htx/Config.lb b/src/mainboard/iwill/dk8_htx/Config.lb index d9bed6ddd7..3bb42e86a5 100644 --- a/src/mainboard/iwill/dk8_htx/Config.lb +++ b/src/mainboard/iwill/dk8_htx/Config.lb @@ -129,8 +129,6 @@ if HAVE_ACPI_TABLES end end -if USE_DCACHE_RAM - if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o @@ -148,7 +146,6 @@ if USE_DCACHE_RAM end end -end if USE_FAILOVER_IMAGE else @@ -178,7 +175,6 @@ else end mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -186,7 +182,6 @@ if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -215,12 +210,10 @@ end mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -229,15 +222,11 @@ end ### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover_failover.lds - end end else if USE_FALLBACK_IMAGE - if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds - end end end @@ -248,16 +237,12 @@ end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject cache_as_ram_auto.o else mainboardinit ./cache_as_ram_auto.inc end -end - ## ## Include the secondary Configuration files ## |