3 files changed, 6 insertions, 54 deletions
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index be3017d27d..fdc7199c70 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -11,30 +11,23 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -212,6 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 2d4efe27a1..45d2e6c10d 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -11,30 +11,23 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "northbridge/amd/amdk8/resourcemap.c"
-
+#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -212,6 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 2d4efe27a1..45d2e6c10d 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -11,30 +11,23 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "northbridge/amd/amdk8/resourcemap.c"
-
+#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -212,6 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-