diff options
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd | 32 | ||||
| -rw-r--r-- | src/mainboard/intel/mtlrvp/chromeos.fmd | 26 |
2 files changed, 25 insertions, 33 deletions
diff --git a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd index 579a7bddc0..bd250f5fab 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd @@ -4,39 +4,33 @@ FLASH 32M { SI_ME } SI_BIOS 23M { - RW_SECTION_A 7M { - VBLOCK_A 64K + RW_SECTION_A 7604K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K + ME_RW_A(CBFS) 4400K } - RW_MISC 1M { + RW_MISC 152K { + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - # The RW_SPD_CACHE region is only used for variants that use DDRx memory. - # It is placed in the common `chromeos.fmd` file because it is only 4K and there - # is free space in the RW_MISC region that cannot be easily reclaimed because - # the RW_SECTION_B must start on the 16M boundary. - RW_SPD_CACHE(PRESERVE) 4K - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 64K + RW_SECTION_B 7604K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K + ME_RW_B(CBFS) 4400K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index 9fc7d7b2c8..22dbff587f 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -1,36 +1,34 @@ FLASH 32M { SI_ALL 9M { SI_DESC 16K - SI_EC 512K SI_ME } SI_BIOS 23M { - RW_SECTION_A 6M { - VBLOCK_A 64K + RW_SECTION_A 7092K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K + ME_RW_A(CBFS) 4400K } - RW_LEGACY(CBFS) 2M - RW_MISC 1M { + RW_MISC 152K { UNIFIED_MRC_CACHE 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K } RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K + RW_NVRAM(PRESERVE) 8K } - RW_SECTION_B 6M { - VBLOCK_B 64K + RW_SECTION_B 7092K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K + ME_RW_B(CBFS) 4400K } + RW_LEGACY(CBFS) 1M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 8M { |