2 files changed, 14 insertions, 74 deletions

diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 0d7c162272..ff018af5f6 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -16,19 +16,14 @@
  */
 
 #include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <arch/romstage.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <southbridge/intel/common/pmclib.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
 
-static void mb_lpc_setup(void)
+void mb_lpc_setup(void)
 {
 	/* Set GPIOs on superio, enable UART */
 	pnp_enter_ext_func_mode(SERIAL_DEV);
@@ -38,40 +33,15 @@ static void mb_lpc_setup(void)
 
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
 	/* IRQ routing */
 	RCBA16(D31IR) = 0x0132;
 	RCBA16(D29IR) = 0x0237;
 }
 
-void mainboard_romstage_entry(void)
+void mb_get_spd_map(u8 spd_map[4])
 {
-	//                          ch0      ch1
-	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
-	u8 boot_path = 0;
-	u8 s3_resume;
-
-	/* Set southbridge and Super I/O GPIOs. */
-	i82801gx_lpc_setup();
-	mb_lpc_setup();
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-	console_init();
-
-	enable_smbus();
-
-	i82801gx_early_init();
-	x4x_early_init();
-
-	s3_resume = southbridge_detect_s3_resume();
-	if (s3_resume)
-		boot_path = BOOT_PATH_RESUME;
-	if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
-		boot_path = BOOT_PATH_WARM_RESET;
-
-	sdram_initialize(boot_path, spd_addrmap);
-
-	x4x_late_init(s3_resume);
-
-	printk(BIOS_DEBUG, "x4x late init complete\n");
-
+	spd_map[0] = 0x50;
+	spd_map[2] = 0x52;
 }
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index b851f98627..71fd87ad74 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -14,23 +14,14 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
-#include <console/console.h>
 #include <southbridge/intel/i82801jx/i82801jx.h>
-#include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <arch/romstage.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
 #include <superio/winbond/common/winbond.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
 
-/* Early mainboard specific GPIO setup.
- * We should use standard gpio.h eventually
- */
-
-static void mb_misc_rcba(void)
+void mb_lpc_setup(void)
 {
 	RCBA32(0x3410) = 0x00060464;
 	RCBA32(RCBA_BUC) &= ~BUC_LAND;
@@ -38,35 +29,14 @@ static void mb_misc_rcba(void)
 	RCBA32(0x341c) = 0xbf7f001f;
 	RCBA32(0x3430) = 0x00000002;
 	RCBA32(0x3f00) = 0x0000000b;
-}
 
-void mainboard_romstage_entry(void)
-{
-	const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
-	u8 boot_path = 0;
-	u8 s3_resume;
-
-	/* Set southbridge and Super I/O GPIOs. */
-	i82801jx_lpc_setup();
-	mb_misc_rcba();
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
 
-	console_init();
-
-	enable_smbus();
-
-	i82801jx_early_init();
-	x4x_early_init();
-
-	s3_resume = southbridge_detect_s3_resume();
-	if (s3_resume)
-		boot_path = BOOT_PATH_RESUME;
-	if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
-		boot_path = BOOT_PATH_WARM_RESET;
-
-	sdram_initialize(boot_path, spd_addrmap);
-
-	x4x_late_init(s3_resume);
-
-	printk(BIOS_DEBUG, "x4x late init complete\n");
+void mb_get_spd_map(u8 spd_map[4])
+{
+	spd_map[0] = 0x50;
+	spd_map[1] = 0x51;
+	spd_map[2] = 0x52;
+	spd_map[3] = 0x53;
 }