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-rw-r--r--src/mainboard/intel/adlrvp/gpio.c2
-rw-r--r--src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c2
-rw-r--r--src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c2
-rw-r--r--src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c2
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c2
7 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 8a04bd959d..d553180541 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -5,7 +5,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Pad configuration in ramstage*/
+/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* SSD1_PWREN CPU SSD1 */
PAD_CFG_GPO(GPP_D14, 1, PLTRST),
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
index 9d17c80d3f..b2e2eeca22 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
@@ -3,7 +3,7 @@
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
-/* Pad configuration in ramstage*/
+/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/*BT_RF_KILL_N*/
PAD_CFG_GPO(GPP_E11, 1, DEEP),
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
index df068659c4..94a6a7970f 100644
--- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
@@ -5,7 +5,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Pad configuration in ramstage*/
+/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* I2S2_SCLK */
PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
index df068659c4..94a6a7970f 100644
--- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
@@ -5,7 +5,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Pad configuration in ramstage*/
+/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* I2S2_SCLK */
PAD_CFG_GPI(GPP_A7, NONE, PLTRST),
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
index 82b3931aaf..27395db402 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
@@ -5,7 +5,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Pad configuration in ramstage*/
+/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* WWAN_WAKE_N */
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index f067af713a..b9fdac8617 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -5,7 +5,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Pad configuration in ramstage*/
+/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* PCH M.2 SSD */
PAD_CFG_GPO(GPP_B16, 1, DEEP),
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
index 889d4e675e..1c007d7bd7 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
@@ -5,7 +5,7 @@
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Pad configuration in ramstage*/
+/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* PCH M.2 SSD */
PAD_CFG_GPO(GPP_B16, 1, DEEP),