1 files changed, 37 insertions, 1 deletions

diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c
index e1f4401b6c..0e1f573a52 100644
--- a/src/mainboard/intel/adlrvp/ramstage.c
+++ b/src/mainboard/intel/adlrvp/ramstage.c
@@ -5,9 +5,11 @@
 #include <console/console.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <soc/gpio_soc_defs.h>
 #include <soc/pci_devs.h>
-
+#include <soc/soc_chip.h>
 #include <drivers/intel/dptf/chip.h>
+#include "board_id.h"
 
 const struct cpu_power_limits limits[] = {
 	/* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */
@@ -49,7 +51,41 @@ void variant_update_power_limits(void)
 	}
 }
 
+static const struct typec_aux_bias_pads pad_config = { GPP_E23, GPP_E22 };
+
+static const struct board_id_iom_port_config {
+	int board_id;
+	enum typec_port_index port;
+} port_config[] = {
+	{ ADL_P_LP4_1,	TYPE_C_PORT_2 },
+	{ ADL_P_LP4_2,	TYPE_C_PORT_2 },
+	{ ADL_P_DDR4_1,	TYPE_C_PORT_2 },
+	{ ADL_P_DDR4_2,	TYPE_C_PORT_2 },
+	{ ADL_P_LP5_1,	TYPE_C_PORT_2 },
+	{ ADL_P_LP5_2,	TYPE_C_PORT_2 },
+	{ ADL_M_LP4,	TYPE_C_PORT_1 },
+	{ ADL_M_LP5,	TYPE_C_PORT_0 },
+};
+
+static void variant_update_typec_init_config(void)
+{
+	/* Skip filling aux bias gpio pads for Windows SKUs */
+	if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC)))
+		return;
+
+	config_t *config = config_of_soc();
+	int board_id = get_board_id();
+	for (int i = 0; i < ARRAY_SIZE(port_config); i++) {
+		if (board_id != port_config[i].board_id)
+			continue;
+
+		memcpy(&config->typec_aux_bias_pads[port_config[i].port], &pad_config,
+			sizeof(pad_config));
+	}
+}
+
 void variant_devtree_update(void)
 {
 	variant_update_power_limits();
+	variant_update_typec_init_config();
 }