2 files changed, 3 insertions, 10 deletions
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index b15f11f4de..f33415741f 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -41,10 +41,10 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices */
-	RCBA32(FD) |= PCH_DISABLE_ALWAYS | PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
+	RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
 
 #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
 	/* Enable Gigabit Ethernet */
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 0759e6252a..3271d630c9 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -63,16 +63,9 @@ void pch_enable_lpc(void)
 	}
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	southbridge_configure_default_intmap();
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 void mainboard_config_superio(void)