diff options
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/jarrell/Config.lb | 14 | ||||
| -rw-r--r-- | src/mainboard/intel/jarrell/Options.lb | 16 | ||||
| -rw-r--r-- | src/mainboard/intel/xe7501devkit/Config.lb | 14 | ||||
| -rw-r--r-- | src/mainboard/intel/xe7501devkit/Options.lb | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/xe7501devkit/bus.h | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/xe7501devkit/ioapic.h | 2 |
6 files changed, 28 insertions, 28 deletions
diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb index 5cea22a5c7..5f0e697232 100644 --- a/src/mainboard/intel/jarrell/Config.lb +++ b/src/mainboard/intel/jarrell/Config.lb @@ -5,7 +5,7 @@ default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -17,18 +17,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -75,7 +75,7 @@ makerule ./auto.inc end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -83,7 +83,7 @@ ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -103,7 +103,7 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb index abc11a5013..0bd5636c5a 100644 --- a/src/mainboard/intel/jarrell/Options.lb +++ b/src/mainboard/intel/jarrell/Options.lb @@ -34,7 +34,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses _RAMBASE @@ -88,7 +88,7 @@ default CONFIG_UDELAY_TSC=1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -110,7 +110,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -139,10 +139,10 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 ## @@ -158,12 +158,12 @@ default HEAP_SIZE=0x8000 ### ### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. +### (coreboot plus bootloader) will live in the boot rom chip. ### default FALLBACK_SIZE=131072 ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -213,7 +213,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb index f03b9c4015..52efe0f326 100644 --- a/src/mainboard/intel/xe7501devkit/Config.lb +++ b/src/mainboard/intel/xe7501devkit/Config.lb @@ -2,7 +2,7 @@ ## BEGIN BOILERPLATE - DO NOT EDIT ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus payload) will live in the boot rom chip. +## (coreboot plus payload) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE # The fallback image uses FALLBACK_SIZE bytes at the end of the ROM @@ -11,7 +11,7 @@ if USE_FALLBACK_IMAGE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else -# The normal image goes at the beginning of the LinuxBIOS ROM region +# The normal image goes at the beginning of the coreboot ROM region # and uses all the remaining space default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) @@ -19,12 +19,12 @@ else end ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -81,7 +81,7 @@ makerule ./auto.inc end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -89,7 +89,7 @@ ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if HAVE_FALLBACK_BOOT if USE_FALLBACK_IMAGE @@ -114,7 +114,7 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb index 0595fe28e5..2f5a71d04c 100644 --- a/src/mainboard/intel/xe7501devkit/Options.lb +++ b/src/mainboard/intel/xe7501devkit/Options.lb @@ -55,7 +55,7 @@ uses USE_FALLBACK_IMAGE uses ROM_SIZE uses ROM_IMAGE_SIZE uses FALLBACK_SIZE -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION ## These are defined in mainboard Config.lb, don't add here uses ROM_SECTION_SIZE @@ -143,7 +143,7 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 ### -### LinuxBIOS layout values +### coreboot layout values ### ## @@ -162,7 +162,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = 0 ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -211,7 +211,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/intel/xe7501devkit/bus.h b/src/mainboard/intel/xe7501devkit/bus.h index 84661ddb36..2378ceaea0 100644 --- a/src/mainboard/intel/xe7501devkit/bus.h +++ b/src/mainboard/intel/xe7501devkit/bus.h @@ -1,7 +1,7 @@ #ifndef XE7501DEVKIT_BUS_H_INCLUDED #define XE7501DEVKIT_BUS_H_INCLUDED -// These were determined by seeing how LinuxBIOS enumerates the various +// These were determined by seeing how coreboot enumerates the various // PCI (and PCI-like) buses on the board. #define PCI_BUS_CHIPSET 0 diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h index 642c04519f..30ae8e7a73 100644 --- a/src/mainboard/intel/xe7501devkit/ioapic.h +++ b/src/mainboard/intel/xe7501devkit/ioapic.h @@ -1,4 +1,4 @@ -// IOAPIC addresses determined by LinuxBIOS enumeration. +// IOAPIC addresses determined by coreboot enumeration. // Someday add functions to get APIC IDs and versions from the chips themselves. #define IOAPIC_ICH3 2 |