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-rw-r--r--src/mainboard/intel/dg43gt/romstage.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 6944b1819e..d3b2b6aec4 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -75,9 +75,6 @@ void mainboard_romstage_entry(unsigned long bist)
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
- /* Disable watchdog timer */
- RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
-
/* Set southbridge and Super I/O GPIOs. */
ich10_enable_lpc();
mb_gpio_init();