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-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb3
-rw-r--r--src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb4
5 files changed, 0 insertions, 13 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 6f282f05a4..1bd4bfec28 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -14,9 +14,6 @@ chip soc/intel/cannonlake
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
- register "usb2_ports[6]" = "USB2_PORT_EMPTY"
- register "usb2_ports[7]" = "USB2_PORT_EMPTY"
- register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index a876994bfa..37b86c6be0 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -15,12 +15,10 @@ chip soc/intel/cannonlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
- register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC6)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC6)"
- register "usb2_ports[13]" = "USB2_PORT_EMPTY"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 4bcfc99083..0754c0735e 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -93,8 +93,6 @@ chip soc/intel/skylake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
- register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
- register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 2dd65c4e8d..d4390b0b29 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -29,8 +29,6 @@ chip soc/intel/tigerlake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
- register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
- register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector
# CPU replacement check
register "CpuReplacementCheck" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index a79bf80073..7a5cae196d 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -22,14 +22,10 @@ chip soc/intel/tigerlake
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
- register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used
- register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used
- register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
- register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
# CPU replacement check