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-rw-r--r--src/mainboard/intel/jarrell/Config.lb213
-rw-r--r--src/mainboard/intel/jarrell/Options.lb242
-rw-r--r--src/mainboard/intel/jarrell/auto.c150
-rw-r--r--src/mainboard/intel/jarrell/chip.h5
-rw-r--r--src/mainboard/intel/jarrell/cmos.layout82
-rw-r--r--src/mainboard/intel/jarrell/debug.c330
-rw-r--r--src/mainboard/intel/jarrell/failover.c46
-rw-r--r--src/mainboard/intel/jarrell/irq_tables.c37
-rw-r--r--src/mainboard/intel/jarrell/jarrell_fixups.c123
-rw-r--r--src/mainboard/intel/jarrell/mainboard.c13
-rw-r--r--src/mainboard/intel/jarrell/microcode_updates.c1563
-rw-r--r--src/mainboard/intel/jarrell/mptable.c293
-rw-r--r--src/mainboard/intel/jarrell/power_reset_check.c12
-rw-r--r--src/mainboard/intel/jarrell/reset.c40
-rw-r--r--src/mainboard/intel/jarrell/watchdog.c138
15 files changed, 3287 insertions, 0 deletions
diff --git a/src/mainboard/intel/jarrell/Config.lb b/src/mainboard/intel/jarrell/Config.lb
new file mode 100644
index 0000000000..adca342a78
--- /dev/null
+++ b/src/mainboard/intel/jarrell/Config.lb
@@ -0,0 +1,213 @@
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=131072
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/E7520
+ device pci_domain 0 on
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 01.0 on end
+ device pci 02.0 on
+ chip southbridge/intel/pxhd # pxhd1
+ device pci 00.0 on end
+ device pci 00.1 on end
+ device pci 00.2 on
+ chip drivers/generic/generic
+ device pci 04.0 on end
+ device pci 04.1 on end
+ end
+ end
+ device pci 00.3 on end
+ end
+ end
+ device pci 06.0 on end
+ chip southbridge/intel/ich5r # ich5r
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 off end
+ device pci 1d.7 on end
+ device pci 1e.0 on
+ chip drivers/ati/ragexl
+ device pci 0c.0 on end
+ end
+ end
+ device pci 1f.0 on
+ chip superio/NSC/pc87427
+ device pnp 2e.0 off end
+ device pnp 2e.2 on
+# io 0x60 = 0x2f8
+# irq 0x70 = 3
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on
+# io 0x60 = 0x3f8
+# irq 0x70 = 4
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 off end
+ device pnp 2e.5 off end
+ device pnp 2e.6 on
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.7 off end
+ device pnp 2e.9 off end
+ device pnp 2e.a off end
+ device pnp 2e.f on end
+ device pnp 2e.10 off end
+ device pnp 2e.14 off end
+ end
+ end
+ device pci 1f.1 on end
+ device pci 1f.2 off end
+ device pci 1f.3 on end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
+ register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
+ register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604_800Mhz # cpu 0
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604_800Mhz # cpu 1
+ device apic 6 on end
+ end
+ end
+end
diff --git a/src/mainboard/intel/jarrell/Options.lb b/src/mainboard/intel/jarrell/Options.lb
new file mode 100644
index 0000000000..a7a5c7288a
--- /dev/null
+++ b/src/mainboard/intel/jarrell/Options.lb
@@ -0,0 +1,242 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_MAX_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses _RAMBASE
+uses CONFIG_GDB_STUB
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_BTEXT
+uses CC
+uses HOSTCC
+uses CROSS_COMPILE
+uses OBJCOPY
+uses MAX_REBOOT_CNT
+uses USE_WATCHDOG_ON_BOOT
+
+
+###
+### Build options
+###
+
+##
+## Because we do the stutter start we need more attempts
+##
+default MAX_REBOOT_CNT=8
+
+##
+## Use the watchdog to break out of a lockup condition
+##
+default USE_WATCHDOG_ON_BOOT=1
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=2097152
+
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Delay timer options
+## Use timer2
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=9
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_LOGICAL_CPUS=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="SE7520JR22D"
+default MAINBOARD_VENDOR= "Intel"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
+#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+default FALLBACK_SIZE=131072
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM=1
+
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+##
+## Don't enable the btext console
+##
+default CONFIG_CONSOLE_BTEXT=0
+
+
+### End Options.lb
+end
diff --git a/src/mainboard/intel/jarrell/auto.c b/src/mainboard/intel/jarrell/auto.c
new file mode 100644
index 0000000000..7e9cd99e96
--- /dev/null
+++ b/src/mainboard/intel/jarrell/auto.c
@@ -0,0 +1,150 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/intel/ich5r/ich5r_early_smbus.c"
+#include "northbridge/intel/E7520/raminit.h"
+#include "superio/NSC/pc87427/pc87427.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "watchdog.c"
+#include "reset.c"
+#include "power_reset_check.c"
+#include "jarrell_fixups.c"
+#include "superio/NSC/pc87427/pc87427_early_init.c"
+#include "northbridge/intel/E7520/memory_initialized.c"
+#include "cpu/x86/bist.h"
+
+#define SIO_GPIO_BASE 0x680
+#define SIO_XBUS_BASE 0x4880
+
+#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
+#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
+
+#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
+#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
+
+/* Beta values: 0x00090800 */
+/* Silver values: 0x000a0900 */
+#define RECVENA_CONFIG 0x000a090a
+#define RECVENB_CONFIG 0x000a090a
+#define DIMM_MAP_LOGICAL 0x0124
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/E7520/raminit.c"
+#include "sdram/generic_sdram.c"
+#include "debug.c"
+
+
+static void main(unsigned long bist)
+{
+ /*
+ *
+ *
+ */
+ static const struct mem_controller mch[] = {
+ {
+ .node_id = 0,
+ .f0 = PCI_DEV(0, 0x00, 0),
+ .f1 = PCI_DEV(0, 0x00, 1),
+ .f2 = PCI_DEV(0, 0x00, 2),
+ .f3 = PCI_DEV(0, 0x00, 3),
+ .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
+ .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
+ }
+ };
+
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ early_mtrr_init();
+ if (memory_initialized()) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ }
+ /* Setup the console */
+ pc87427_disable_dev(CONSOLE_SERIAL_DEV);
+ pc87427_disable_dev(HIDDEN_SERIAL_DEV);
+ pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ /* Enable Serial 2 lines instead of GPIO */
+ outb(0x2c, 0x2e);
+ outb((inb(0x2f) & (~1<<1)), 0x2f);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
+
+ pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
+ xbus_cfg(PC87427_XBUS_DEV);
+
+ /* MOVE ME TO A BETTER LOCATION !!! */
+ /* config LPC decode for flash memory access */
+ device_t dev;
+ dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
+ if (dev == PCI_DEV_INVALID) {
+ die("Missing ich5?");
+ }
+ pci_write_config32(dev, 0xe8, 0x00000000);
+ pci_write_config8(dev, 0xf0, 0x00);
+
+#if 0
+ print_pci_devices();
+#endif
+ enable_smbus();
+#if 0
+// dump_spd_registers(&cpu[0]);
+ int i;
+ for(i = 0; i < 1; i++) {
+ dump_spd_registers();
+ }
+#endif
+ disable_watchdogs();
+ power_down_reset_check();
+// dump_ipmi_registers();
+ mainboard_set_e7520_leds();
+ sdram_initialize(sizeof(mch)/sizeof(mch[0]), mch);
+ ich5_watchdog_on();
+#if 0
+ dump_pci_devices();
+#endif
+#if 0
+ dump_pci_device(PCI_DEV(0, 0x00, 0));
+ dump_bar14(PCI_DEV(0, 0x00, 0));
+#endif
+
+#if 0 // temporarily disabled
+ /* Check the first 1M */
+// ram_check(0x00000000, 0x000100000);
+// ram_check(0x00000000, 0x000a0000);
+ ram_check(0x00100000, 0x01000000);
+ /* check the first 1M in the 3rd Gig */
+ ram_check(0x30100000, 0x31000000);
+#if 0
+ ram_check(0x00000000, 0x02000000);
+#endif
+
+#endif
+#if 0
+ while(1) {
+ hlt();
+ }
+#endif
+}
diff --git a/src/mainboard/intel/jarrell/chip.h b/src/mainboard/intel/jarrell/chip.h
new file mode 100644
index 0000000000..7cc59091bd
--- /dev/null
+++ b/src/mainboard/intel/jarrell/chip.h
@@ -0,0 +1,5 @@
+struct chip_operations mainboard_intel_jarrell_ops;
+
+struct mainboard_intel_jarrell_config {
+ int nothing;
+};
diff --git a/src/mainboard/intel/jarrell/cmos.layout b/src/mainboard/intel/jarrell/cmos.layout
new file mode 100644
index 0000000000..71387a2e4b
--- /dev/null
+++ b/src/mainboard/intel/jarrell/cmos.layout
@@ -0,0 +1,82 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 376 r 0 reserved_memory
+376 1 e 1 power_up_watchdog
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 2 hyper_threading
+397 1 e 1 pxhd_bus_speed_100
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 reserved_memory
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c
new file mode 100644
index 0000000000..5546421156
--- /dev/null
+++ b/src/mainboard/intel/jarrell/debug.c
@@ -0,0 +1,330 @@
+#define SMBUS_MEM_DEVICE_START 0x50
+#define SMBUS_MEM_DEVICE_END 0x57
+#define SMBUS_MEM_DEVICE_INC 1
+
+static void print_reg(unsigned char index)
+{
+ unsigned char data;
+
+ outb(index, 0x2e);
+ data = inb(0x2f);
+ print_debug("0x");
+ print_debug_hex8(index);
+ print_debug(": 0x");
+ print_debug_hex8(data);
+ print_debug("\r\n");
+ return;
+}
+
+static void xbus_en(void)
+{
+ /* select the XBUS function in the SIO */
+ outb(0x07, 0x2e);
+ outb(0x0f, 0x2f);
+ outb(0x30, 0x2e);
+ outb(0x01, 0x2f);
+ return;
+}
+
+static void setup_func(unsigned char func)
+{
+ /* select the function in the SIO */
+ outb(0x07, 0x2e);
+ outb(func, 0x2f);
+ /* print out the regs */
+ print_reg(0x30);
+ print_reg(0x60);
+ print_reg(0x61);
+ print_reg(0x62);
+ print_reg(0x63);
+ print_reg(0x70);
+ print_reg(0x71);
+ print_reg(0x74);
+ print_reg(0x75);
+ return;
+}
+
+static void siodump(void)
+{
+ int i;
+ unsigned char data;
+
+ print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ for (i=0x10; i<=0x2d; i++) {
+ print_reg((unsigned char)i);
+ }
+#if 0
+ print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ setup_func(0x0f);
+ for (i=0xf0; i<=0xff; i++) {
+ print_reg((unsigned char)i);
+ }
+
+ print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ setup_func(0x03);
+ print_reg(0xf0);
+
+ print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ setup_func(0x02);
+ print_reg(0xf0);
+
+#endif
+ print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ setup_func(0x07);
+ for (i=0xf0; i<=0xf8; i++) {
+ print_reg((unsigned char)i);
+ }
+ print_debug("\r\n*** GPIO VALUES ***\r\n");
+ data = inb(0x68a);
+ print_debug("\r\nGPDO 4: 0x");
+ print_debug_hex8(data);
+ data = inb(0x68b);
+ print_debug("\r\nGPDI 4: 0x");
+ print_debug_hex8(data);
+ print_debug("\r\n");
+
+#if 0
+
+ print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ setup_func(0x0a);
+ print_reg(0xf0);
+
+ print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ setup_func(0x09);
+ print_reg(0xf0);
+ print_reg(0xf1);
+
+ print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ setup_func(0x10);
+ print_reg(0xf0);
+ print_reg(0xf1);
+ print_reg(0xf3);
+ print_reg(0xf6);
+ print_reg(0xf7);
+ print_reg(0xfe);
+ print_reg(0xff);
+
+ print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ setup_func(0x14);
+ print_reg(0xf0);
+#endif
+ return;
+}
+
+static void print_debug_pci_dev(unsigned dev)
+{
+ print_debug("PCI: ");
+ print_debug_hex8((dev >> 16) & 0xff);
+ print_debug_char(':');
+ print_debug_hex8((dev >> 11) & 0x1f);
+ print_debug_char('.');
+ print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+ }
+}
+
+static void dump_pci_device(unsigned dev)
+{
+ int i;
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+
+ for(i = 0; i <= 255; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ }
+}
+
+static void dump_bar14(unsigned dev)
+{
+ int i;
+ unsigned long bar;
+
+ print_debug("BAR 14 Dump\r\n");
+
+ bar = pci_read_config32(dev, 0x14);
+ for(i = 0; i <= 0x300; i+=4) {
+#if 0
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+#endif
+ if((i%4)==0) {
+ print_debug("\r\n");
+ print_debug_hex16(i);
+ print_debug_char(' ');
+ }
+ print_debug_hex32(read32(bar + i));
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+}
+
+static void dump_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
+}
+
+#if 0
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+ int i;
+ print_debug("\r\n");
+ for(i = 0; i < 4; i++) {
+ unsigned device;
+ device = ctrl->channel0[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".0: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ device = ctrl->channel1[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".1: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ }
+}
+#endif
+
+void dump_spd_registers(void)
+{
+ unsigned device;
+ device = SMBUS_MEM_DEVICE_START;
+ while(device <= SMBUS_MEM_DEVICE_END) {
+ int status = 0;
+ int i;
+ print_debug("\r\n");
+ print_debug("dimm ");
+ print_debug_hex8(device);
+
+ for(i = 0; (i < 256) ; i++) {
+ unsigned char byte;
+ if ((i % 16) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(i);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, i);
+ if (status < 0) {
+ print_debug("bad device: ");
+ print_debug_hex8(-status);
+ print_debug("\r\n");
+ break;
+ }
+ print_debug_hex8(status);
+ print_debug_char(' ');
+ }
+ device += SMBUS_MEM_DEVICE_INC;
+ print_debug("\n");
+ }
+}
+
+void dump_ipmi_registers(void)
+{
+ unsigned device;
+ device = 0x42;
+ while(device <= 0x42) {
+ int status = 0;
+ int i;
+ print_debug("\r\n");
+ print_debug("ipmi ");
+ print_debug_hex8(device);
+
+ for(i = 0; (i < 8) ; i++) {
+ unsigned char byte;
+ status = smbus_read_byte(device, 2);
+ if (status < 0) {
+ print_debug("bad device: ");
+ print_debug_hex8(-status);
+ print_debug("\r\n");
+ break;
+ }
+ print_debug_hex8(status);
+ print_debug_char(' ');
+ }
+ device += SMBUS_MEM_DEVICE_INC;
+ print_debug("\n");
+ }
+}
diff --git a/src/mainboard/intel/jarrell/failover.c b/src/mainboard/intel/jarrell/failover.c
new file mode 100644
index 0000000000..5029d98611
--- /dev/null
+++ b/src/mainboard/intel/jarrell/failover.c
@@ -0,0 +1,46 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "pc80/mc146818rtc_early.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/intel/E7520/memory_initialized.c"
+
+static unsigned long main(unsigned long bist)
+{
+ /* Did just the cpu reset? */
+ if (memory_initialized()) {
+ if (last_boot_normal()) {
+ goto normal_image;
+ } else {
+ goto cpu_reset;
+ }
+ }
+
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
+}
diff --git a/src/mainboard/intel/jarrell/irq_tables.c b/src/mainboard/intel/jarrell/irq_tables.c
new file mode 100644
index 0000000000..75071c131a
--- /dev/null
+++ b/src/mainboard/intel/jarrell/irq_tables.c
@@ -0,0 +1,37 @@
+/* PCI: Interrupt Routing Table found at 0x40114180 size = 320 */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ 0x52495024, /* u32 signature */
+ 0x0100, /* u16 version */
+ 320, /* u16 Table size 32+(16*devices) */
+ 0x00, /* u8 Bus 0 */
+ 0xf8, /* u8 Device 1, Function 0 */
+ 0x0000, /* u16 reserve IRQ for PCI */
+ 0x8086, /* u16 Vendor */
+ 0x24d0, /* Device ID */
+ 0x00000000, /* u32 miniport_data */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x38, /* u8 checksum - mod 256 checksum must give zero */
+ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, 0x08, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
+ {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
+ {0x00, 0xe8, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00},
+ {0x02, 0x20, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
+ {0x03, 0x28, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
+ {0x04, 0x60, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00},
+ {0x02, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x04, 0x00},
+ {0x02, 0x10, {{0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x05, 0x00},
+ {0x02, 0x18, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}}, 0x06, 0x00},
+ {0x03, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x01, 0x00},
+ {0x03, 0x10, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}}, 0x02, 0x00},
+ {0x03, 0x18, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x03, 0x00},
+ {0x00, 0x10, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
+ {0x00, 0x18, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
+ {0x00, 0x20, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
+ {0x00, 0x28, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
+ {0x00, 0x30, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00},
+ {0x00, 0x38, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00, 0x00}
+ }
+};
diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c
new file mode 100644
index 0000000000..d8c694b4af
--- /dev/null
+++ b/src/mainboard/intel/jarrell/jarrell_fixups.c
@@ -0,0 +1,123 @@
+#include <arch/romcc_io.h>
+
+static void mch_reset(void)
+{
+ device_t dev;
+ unsigned long value, base;
+ dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
+ if (dev != PCI_DEV_INVALID) {
+ /* I/O space is always enables */
+
+ /* Set gpio base */
+ pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
+ base = ICH5_GPIOBASE;
+
+ /* Enable GPIO Bar */
+ value = pci_read_config32(dev, 0x5c);
+ value |= 0x10;
+ pci_write_config32(dev, 0x5c, value);
+
+ /* Set GPIO 19 mux to IO usage */
+ value = inl(base);
+ value |= (1 <<19);
+ outl(value, base);
+
+ /* Pull GPIO 19 low */
+ value = inl(base + 0x0c);
+ value &= ~(1 << 19);
+ outl(value, base + 0x0c);
+ }
+ return;
+}
+
+
+
+static void mainboard_set_e7520_pll(unsigned bits)
+{
+ uint16_t gpio_index;
+ uint8_t data;
+ device_t dev;
+
+ /* currently only handle the Jarrell/PC87427 case */
+ dev = PC87427_GPIO_DEV;
+
+
+ pnp_set_logical_device(dev);
+ gpio_index = pnp_read_iobase(dev, 0x60);
+
+ /* select SIO GPIO port 4, pin 2 */
+ pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
+ /* set to push-pull, enable output */
+ pnp_write_config(dev, PC87427_GPCFG1, 0x03);
+
+ /* select SIO GPIO port 4, pin 4 */
+ pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
+ /* set to push-pull, enable output */
+ pnp_write_config(dev, PC87427_GPCFG1, 0x03);
+
+ /* set gpio 42,44 signal levels */
+ data = inb(gpio_index + PC87427_GPDO_4);
+ if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
+ print_debug("set_pllsel: correct settings detected!\r\n");
+ return; /* settings already configured */
+ } else {
+ outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
+ /* reset */
+ print_debug("set_pllsel: settings adjusted, now resetting...\r\n");
+ // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
+// mch_reset();
+ full_reset();
+ }
+ return;
+}
+
+
+static void mainboard_set_e7520_leds(void)
+{
+ uint8_t cnt;
+ uint8_t data;
+ device_t dev;
+
+ /* currently only handle the Jarrell/PC87427 case */
+ dev = PC87427_GPIO_DEV;
+
+ pnp_set_logical_device(dev);
+
+ /* enable */
+ outb(0x30, 0x2e);
+ outb(0x01, 0x2f);
+ outb(0x2d, 0x2e);
+ outb(0x01, 0x2f);
+
+ /* Set auto mode for dimm leds and post */
+ outb(0xf0,0x2e);
+ outb(0x70,0x2f);
+ outb(0xf4,0x2e);
+ outb(0x30,0x2f);
+ outb(0xf5,0x2e);
+ outb(0x88,0x2f);
+ outb(0xf6,0x2e);
+ outb(0x00,0x2f);
+ outb(0xf7,0x2e);
+ outb(0x90,0x2f);
+ outb(0xf8,0x2e);
+ outb(0x00,0x2f);
+
+ /* Turn the leds off */
+ outb(0x00,0x88);
+ outb(0x00,0x90);
+
+ /* Disable the ports */
+ outb(0xf5,0x2e);
+ outb(0x00,0x2f);
+ outb(0xf7,0x2e);
+ outb(0x00,0x2f);
+ outb(0xf4,0x2e);
+ outb(0x00,0x2f);
+
+ return;
+}
+
+
+
+
diff --git a/src/mainboard/intel/jarrell/mainboard.c b/src/mainboard/intel/jarrell/mainboard.c
new file mode 100644
index 0000000000..9b25e0adeb
--- /dev/null
+++ b/src/mainboard/intel/jarrell/mainboard.c
@@ -0,0 +1,13 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <arch/io.h>
+#include "chip.h"
+
+struct chip_operations mainboard_intel_e7520_ops = {
+ CHIP_NAME("Intel Jarell mainboard ")
+};
+
diff --git a/src/mainboard/intel/jarrell/microcode_updates.c b/src/mainboard/intel/jarrell/microcode_updates.c
new file mode 100644
index 0000000000..54daab0779
--- /dev/null
+++ b/src/mainboard/intel/jarrell/microcode_updates.c
@@ -0,0 +1,1563 @@
+/* WARNING - Intel has a new data structure that has variable length
+ * microcode update lengths. They are encoded in int 8 and 9. A
+ * dummy header of nulls must terminate the list.
+ */
+
+static const unsigned int microcode_updates[] __attribute__ ((aligned(16))) = {
+ /*
+ Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000.
+ These microcode updates are distributed for the sole purpose of
+ installation in the BIOS or Operating System of computer systems
+ which include an Intel P6 family microprocessor sold or distributed
+ to or by you. You are authorized to copy and install this material
+ on such systems. You are not authorized to use this material for
+ any other purpose.
+ */
+
+ /* M1DF340E.TXT - Noconoa D-0 */
+
+
+ 0x00000001, /* Header Version */
+ 0x0000000e, /* Patch ID */
+ 0x05042004, /* DATE */
+ 0x00000f34, /* CPUID */
+ 0x9b18561d, /* Checksum */
+ 0x00000001, /* Loader Version */
+ 0x0000001d, /* Platform ID */
+ 0x000017d0, /* Data size */
+ 0x00001800, /* Total size */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+ 0x00000000, /* reserved */
+ 0x9fbf327a,
+ 0x2b41b451,
+ 0xb0a79cab,
+ 0x6b62b8fd,
+ 0xc953d679,
+ 0x1e462145,
+ 0x59d96ae5,
+ 0xb90dfc00,
+ 0x4f6bd233,
+ 0xa8dda234,
+ 0xb96b5eb7,
+ 0x588fc98f,
+ 0xdd59a87c,
+ 0xb038ad4c,
+ 0x338af84c,
+ 0x44842e0d,
+ 0x2e664aa6,
+ 0xd46497b7,
+ 0xddbcd376,
+ 0xd86dd62a,
+ 0x27ceec6e,
+ 0xb089ff2e,
+ 0xfc549965,
+ 0x556f5b78,
+ 0xa8c4732c,
+ 0x0969180d,
+ 0x14a346e8,
+ 0x561a91b3,
+ 0x1cd21cde,
+ 0xd09d06bc,
+ 0x3a4cae91,
+ 0x5d23fa54,
+ 0x43747e8d,
+ 0x19ff0547,
+ 0xdae0e17a,
+ 0xc16bab85,
+ 0x2364fea6,
+ 0x8508f3c6,
+ 0x598ca70f,
+ 0x72fb0579,
+ 0x24c28f46,
+ 0xed19ad6b,
+ 0xcd6206fe,
+ 0xe3d091e8,
+ 0xb7f1f9f1,
+ 0x501c1c77,
+ 0x5fdda272,
+ 0xbdc8301b,
+ 0x64b200ea,
+ 0xb8460b09,
+ 0x26d125ea,
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+ 0x05fec000,
+ 0x21b2478a,
+ 0x7efa9d65,
+ 0x4b7d2ce1,
+ 0x4cdb4f14,
+ 0x1a41a5c4,
+ 0x424d94f3,
+ 0xf364aa6e,
+ 0xe003899b,
+ 0x2284d34e,
+ 0xc235c39c,
+ 0xd0e54c8d,
+ 0x969ed32e,
+ 0xadca1e41,
+ 0x1cf5dd48,
+ 0xfeaee739,
+ 0x8aa95f56,
+ 0x79123691,
+ 0xa8d5e6df,
+ 0x14941574,
+ 0xa002f08e,
+ 0x81125113,
+ 0x835eac03,
+ 0x23e1df47,
+ 0x5f3856fe,
+ 0xf5bc6869,
+ 0xce6f65f1,
+ 0xf8f88627,
+ 0xb0a74080,
+ 0xc2c67512,
+ 0x47510b62,
+ 0x757a8619,
+ 0xd358a6cf,
+ 0xefd36be3,
+ 0x0d8e6ebe,
+ 0xe244e367,
+ 0xdaf5202b,
+ 0x9da43b72,
+ 0x799510b2,
+ 0x7aba0824,
+ 0xc9375579,
+ 0x430b0595,
+ 0x49aeff96,
+ 0x471a76a4,
+ 0x6d902adb,
+ 0xcd87aab5,
+ 0x7767a00d,
+ 0x5960ca6e,
+ 0x4f8ef870,
+ 0x309fa8bf,
+ 0x46d14c6b,
+ 0xd75ceaf2,
+ 0x59d42f82,
+ 0xd282a8bc,
+ 0x52639643,
+ 0xd7cf10ce,
+ 0x943a78f5,
+ 0xc69e88e3,
+ 0x10eeeba0,
+ 0xcafc5c65,
+ 0xff74b46a,
+ 0xf79f4d9c,
+ 0x2630e51a,
+ 0x7e2214b4,
+ 0x880f701b,
+ 0xd93cce83,
+ 0xc3c79a30,
+ 0xa0a02241,
+ 0x33b91b39,
+ 0x11fcc620,
+ 0xc9ba6612,
+ 0xe7443db4,
+ 0x3cc12aa5,
+ 0x157f6b71,
+ 0x5c24d7b8,
+ 0x19236745,
+ 0x9db789d6,
+ 0x5c2d0dfd,
+ 0xea6d256f,
+ 0x6d7b3e15,
+ 0xe7334d29,
+ 0xf6997706,
+ 0x30aefa11,
+ 0x75b11c2f,
+ 0x66d9f586,
+ 0x16c2c53e,
+ 0x537a5647,
+ 0xb49df107,
+ 0xf502f5c2,
+ 0x8a6417a1,
+ 0xa1ff6fed,
+ 0xdd7a388c,
+ 0x484bc008,
+ 0x96aeb4df,
+ 0x7e5da879,
+ 0x39ba7899,
+ 0x945096f4,
+ 0xaca0677a,
+ 0x3aab6837,
+ 0x693eb6ae,
+ 0xd2769858,
+ 0xf8c3a848,
+ 0x3d416f0d,
+ 0xc827d5b8,
+ 0x634a0142,
+ 0x95307840,
+ 0x38598312,
+ 0xebd78517,
+ 0x9759f546,
+ 0x96cae151,
+ 0x41cbbc4a,
+ 0xd8414d28,
+ 0x0109dae8,
+ 0xfcaa2c27,
+ 0x0d4fe4eb,
+ 0x4347492e,
+ 0x3c16415e,
+ 0xe491356a,
+ 0x61b4e63f,
+ 0x00ede80d,
+ 0xe1fcdfe5,
+ 0xfa4652e8,
+ 0x1fc3ba51,
+ 0x88951c66,
+ 0x9a692f49,
+ 0xe18779f7,
+ 0xb4139fe4,
+ 0x8d9eaa67,
+ 0x53543af7,
+ 0x528fbc3d,
+ 0x18db3cc7,
+ 0x56c5f946,
+ 0xe70a19b3,
+ 0x13fceeee,
+ 0x73b311c8,
+ 0xbed6fe39,
+ 0xd92e42e7,
+ 0xee11ab04,
+ 0x20e4eec8,
+ 0xca96264f,
+ 0x948e9472,
+ 0x609ca9b0,
+ 0xa08c2aad,
+ 0xfd2504f9,
+ 0x36cf63ae,
+ 0xe0734470,
+ 0x652751e7,
+ 0x642273d0,
+ 0x9823fbe7,
+ 0x6824fe6a,
+ 0xe80ac838,
+ 0x18846710,
+ 0xfec2c7aa,
+ 0xd80a48b4,
+ 0xa66fe74c,
+ 0x3f30c5dc,
+ 0x227433b1,
+ 0x83c4d631,
+ 0x706c636a,
+ 0x138b0fad,
+ 0xe56524c0,
+ 0xb2ac11f9,
+ 0xad1799ce,
+ 0x7ad15722,
+ 0x1f163bb9,
+ 0xd94d13e6,
+ 0xba486e31,
+ 0x4147dc40,
+ 0xf294535b,
+ 0xf3795177,
+ 0x6cc4c80e,
+ 0xce535635,
+ 0xaa7227f5,
+ 0xf08a7bf1,
+ 0x04abff71,
+ 0xc9fa751c,
+ 0xf507bee7,
+ 0x36461342,
+ 0x257fdb9c,
+ 0x8e7e5088,
+ 0x82c48383,
+ 0xbca8a03a,
+ 0x981b4944,
+ 0x82761269,
+ 0x304b3d32,
+ 0xf3e469b2,
+ 0x3a26b2af,
+ 0xccbbba89,
+ 0xc28a2b71,
+ 0xa69cef0d,
+ 0xbcb33016,
+ 0x5b682012,
+ 0xfcdf7e05,
+ 0x0b0ba583,
+ 0x499ca677,
+ 0x4fba9f8e,
+ 0x7b76bc65,
+ 0x2fc75e51,
+ 0xc15ddfe9,
+ 0x861d4c9c,
+ 0xb8a93900,
+ 0x92bd9e86,
+ 0x5ff6d34f,
+ 0x2709acde,
+ 0x4e297037,
+ 0x0e1d5d01,
+ 0xf17f9166,
+ 0x4444d54c,
+ 0xea9aa934,
+ 0xb5a8ab82,
+ 0x501c04e6,
+ 0xe7c53a5e,
+ 0xb3af5520,
+ 0x6fa0a711,
+ 0xd10ae8c8,
+ 0xbca08561,
+ 0xdef0f8dc,
+ 0x2b00a8da,
+ 0x194cfec5,
+ 0x53cced19,
+ 0xd882fd4c,
+ 0xd2a1f062,
+ 0xbd9c92ab,
+ 0x11faa9c4,
+ 0x6b81821f,
+ 0xd50e6f83,
+ 0x9e6a865e,
+ 0x6af4288a,
+ 0xc7474730,
+ 0xa3ee94f6,
+ 0x53f3a99d,
+ 0xfe59024c,
+ 0x93372281,
+ 0x02abbc57,
+ 0x97fc1888,
+ 0xbc99a04c,
+ 0xd8f811a7,
+ 0x4687ef67,
+ 0xd28b56de,
+ 0x70c55613,
+ 0xbbad7b20,
+ 0xd8ef8c62,
+ 0xcbd82566,
+ 0x4b42df32,
+ 0x08ec3009,
+ 0x75815b67,
+ 0x72bacd00,
+ 0xab7f376a,
+ 0x42eafc17,
+ 0x4044abef,
+ 0xdd3e7e25,
+ 0xc6a85884,
+ 0x072e2f0c,
+ 0x68b1f04b,
+ 0xe406c8aa,
+ 0x882f5d33,
+ 0xaa29b242,
+ 0xe5623462,
+ 0xc83e4127,
+ 0x4a7052bc,
+ 0x0a28ad40,
+ 0x754b0cc7,
+ 0x2aad9413,
+ 0x6b529f22,
+ 0x07ddc99b,
+ 0x9cd5e160,
+ 0x7ff454c5,
+ 0x7ab0fa49,
+ 0x330dc0f7,
+ 0x35f7c492,
+ 0xfa234caf,
+ 0xebd6def4,
+ 0xea7d0b21,
+ 0x5bf95b14,
+ 0x0df1a519,
+ 0x2ec447ac,
+ 0xd6e80c4c,
+ 0xc6cba5ff,
+ 0x74424b66,
+ 0x994f29ff,
+ 0x133beb2e,
+ 0xbf4a6652,
+ 0x4308b5da,
+ 0x11fe0718,
+ 0xca296045,
+ 0x949be826,
+ 0x6e2c3fb8,
+ 0xb850aa5c,
+ 0x33f58121,
+ 0x694d49c0,
+ 0x90e404d8,
+ 0x7704a82f,
+ 0x4c55d386,
+ 0xeb7593e2,
+ 0x1550ecf0,
+ 0x9755c436,
+ 0x00e2bd8c,
+ 0x819b4cb6,
+ 0x57047356,
+ 0xca7f96bb,
+ 0xd21846d3,
+ 0xe75c8b6b,
+ 0x7c64db6a,
+ 0x66807671,
+ 0x42afbdac,
+ 0x898a62a1,
+ 0x352b4728,
+ 0xa01ab76a,
+ 0x3ecaa8ad,
+ 0x857e137f,
+ 0x7425aa2c,
+ 0x59820cd5,
+ 0x6cabe70e,
+ 0xdf2b5075,
+ 0x80d9ace0,
+ 0x87a585a2,
+ 0xa8aa2961,
+ 0xc78ae53d,
+ 0xad2fe51a,
+ 0x12fc4d3b,
+ 0xc2586e62,
+ 0x3f9af3c1,
+ 0x31aaca0e,
+ 0x90de6dfa,
+ 0xe8423a5d,
+ 0x3473b38f,
+ 0xb306a21c,
+ 0x25c329db,
+ 0xa63f49ce,
+ 0xd64d55a5,
+ 0xf22cd1fa,
+ 0x5bb1371f,
+ 0xa9548a1e,
+ 0xb7e2103f,
+ 0xfafd86f1,
+ 0x04f18888,
+ 0xef929aed,
+ 0xc7f32159,
+ 0x187d353c,
+ 0xace75d6e,
+ 0x7c8a9d00,
+ 0xedc5203e,
+ 0x4f8ad5e8,
+ 0x270a3740,
+ 0x136db4c5,
+ 0x4d745554,
+ 0xe834508e,
+ 0x1e7971ec,
+ 0x52af33bd,
+ 0xc6be41f2,
+ 0x06bf9120,
+ 0x56c34b9f,
+ 0x27dda918,
+ 0xa873d58d,
+ 0xaba2b6d2,
+ 0x46ee0a64,
+ 0xf71e6893,
+ 0x6dadbe93,
+ 0xc2dd2fc3,
+ 0xe07ef64c,
+ 0x2a17ea62,
+ 0x918e4d24,
+ 0x226ee1fd,
+ 0x98b6f003,
+ 0x75dfe5ba,
+ 0xb9783d6e,
+ 0x2847a098,
+ 0x3b5f8fed,
+ 0x4a264321,
+ 0xf0989f25,
+ 0xea2896e7,
+ 0x62830aaf,
+ 0x7ebb47eb,
+ 0x7b990fc2,
+ 0xcfe59d2c,
+ 0xdf7b0cec,
+ 0xee2bb918,
+ 0x2e107193,
+ 0x2ffcc92b,
+ 0x56c8d7fb,
+ 0x6d9596a2,
+ 0xdbade8c2,
+ 0x96bbd09c,
+ 0x3be88ddb,
+ 0x25788736,
+ 0xf42e08aa,
+ 0x2ace1c30,
+ 0x04b3283b,
+ 0x42abff1c,
+ 0x9109f92e,
+ 0xf44f974c,
+ 0x69de015b,
+ 0xcb5be1a3,
+ 0x42006ec8,
+ 0xf9f7bbae,
+ 0x0e498747,
+ 0xe64f42e5,
+ 0xbdd9769a,
+ 0xbfefe3ed,
+ 0x1cf0b302,
+ 0x304b38bb,
+ 0x6fe98e02,
+ 0x198560f0,
+ 0x5f323a6b,
+ 0x32d80d5b,
+ 0xa02926cf,
+ 0x749673f7,
+ 0xdc5b89eb,
+ 0xd7e59060,
+ 0x08f0c0c8,
+ 0x05f2b242,
+ 0x41c621b9,
+ 0x0f9d75e4,
+ 0xc10fb771,
+ 0x723e2009,
+ 0x609c716a,
+ 0xc1a4321c,
+ 0x2a585c54,
+ 0x512a2333,
+ 0x9b83b957,
+ 0xaa789a88,
+ 0xf77108d3,
+ 0x9d5dff9c,
+ 0x3516bf33,
+ 0x2553ec5e,
+ 0x5b9cd3fc,
+ 0xc4c8576c,
+ 0xf49a4004,
+ 0xbc0e4aa0,
+ 0x23dd6368,
+ 0x41ed272f,
+ 0x2665d6de,
+ 0x51ef3bc7,
+ 0x5a7bbe62,
+ 0x11711c5a,
+ 0xd750fbb8,
+ 0xfe0b186c,
+ 0x1cacecb5,
+ 0x4c3e6cff,
+ 0xa9166568,
+ 0x5c28eae4,
+ 0x916df88f,
+ 0x3581d00f,
+ 0xfa85b4c6,
+ 0xade872df,
+ 0xbd2d75c7,
+ 0x35a17396,
+ 0xbe2f15ec,
+ 0x2ed3dc19,
+ 0xfc8ccfb4,
+ 0xd72224ca,
+ 0x5b467c42,
+ 0x05740237,
+ 0xc90cc5af,
+ 0x7ee94bb7,
+ 0x341ce345,
+ 0xf6d5c608,
+ 0x54395b3e,
+ 0x86671dc1,
+ 0xa012736f,
+ 0xece35f7e,
+ 0x98b029cf,
+ 0xc3bac321,
+ 0xa83bb90f,
+ 0x4e98f460,
+ 0x172ad9d0,
+ 0x0ddf428b,
+ 0xc732c52e,
+ 0x751bb0b1,
+ 0x7e635e70,
+ 0xcf083db0,
+ 0xf7665ffb,
+ 0xd10b7314,
+ 0x0a0915c2,
+ 0x9b708e96,
+ 0xdd6641dc,
+ 0xd3c5503f,
+ 0x99fcad3c,
+ 0x7f7cdac4,
+ 0xacf81c45,
+ 0xbb9ac1aa,
+ 0x9edba02a,
+ 0xd2674351,
+ 0x655d6e1a,
+ 0x316eb98b,
+ 0xef0da1b0,
+ 0x230268a6,
+ 0xa3d15e0c,
+ 0x1af0fe7a,
+ 0x545a1440,
+ 0x58ebb256,
+ 0x3004ba86,
+ 0x5625f280,
+ 0x31fba6e9,
+ 0x0d816494,
+ 0x26c6f165,
+ 0xe871e8de,
+ 0xe1d7f6d4,
+ 0x023760f2,
+ 0x440f27af,
+ 0x728ba35f,
+ 0x17ce346a,
+ 0x3a11f0d1,
+ 0x6207d713,
+ 0x20f84bc8,
+ 0xd6bbd3c5,
+ 0x54e23e98,
+ 0x4d55a3f4,
+ 0x0bcb2af5,
+ 0xd669176e,
+ 0x587e3dfc,
+ 0x76c2cb8f,
+ 0xf76cf120,
+ 0x4d5802b4,
+ 0x5c14c2f2,
+ 0x75343fec,
+ 0xdd66b18c,
+ 0xc71afb83,
+ 0x98443a88,
+ 0xdefbb711,
+ 0xfdb0d451,
+ 0x26c463d8,
+ 0xbeb59073,
+ 0xea637d70,
+ 0x75ac392c,
+ 0x8911a2c2,
+ 0xea8a08c4,
+ 0xb17c6b41,
+ 0x95187ba1,
+ 0xca82b4e0,
+ 0x47b9b7c5,
+ 0xd07c16f8,
+ 0x0b008289,
+ 0x1638d750,
+ 0x1c67341e,
+ 0x3d1c7fcd,
+ 0x773a6217,
+ 0x402ce582,
+ 0xb391379f,
+ 0x5f329458,
+ 0x7df3edc8,
+ 0x939cb659,
+ 0x54cec0df,
+ 0x32a63ce6,
+ 0x5473cd21,
+ 0x5399ca04,
+ 0xd48fec8d,
+ 0x184a35dd,
+ 0x0259889e,
+ 0xf5de1e03,
+ 0xf637e932,
+ 0xdac59987,
+ 0x3482e9ef,
+ 0xc4b0d39c,
+ 0xc1703b84,
+ 0x82783cc5,
+ 0x609005de,
+ 0xa6f4b2ec,
+ 0x2cfd9aee,
+ 0xeeba8f38,
+ 0x4f1bd205,
+ 0xa1f30232,
+ 0x79587a9a,
+ 0x9032d2a0,
+ 0x3f2a3667,
+ 0x0be30687,
+ 0xab67f3b2,
+ 0x5e7952bd,
+ 0x1055730a,
+ 0x7326e2ef,
+ 0x4e90bafe,
+ 0x40098ae4,
+ 0xbc8b3245,
+ 0xac40eacf,
+ 0x990d0b6a,
+ 0xcc285b9d,
+ 0x1f84b128,
+ 0x3d3baa7e,
+ 0xa25b70c3,
+ 0x24ad4c19,
+ 0xea67f99e,
+ 0x0692f3a5,
+ 0x282a5acd,
+ 0x507aa6fe,
+ 0xb73af27f,
+ 0x915227cc,
+ 0xe3c0fb17,
+ 0x234d8772,
+ 0x5038947d,
+ 0xa6770fb2,
+ 0x0cbe5619,
+ 0x62310604,
+ 0x577f3820,
+ 0xa0f465d0,
+ 0xd58e64e3,
+ 0xf9c7c1a0,
+ 0x02366336,
+ 0x7514c9ff,
+ 0xc80e7468,
+ 0x31c55e4c,
+ 0x64f2ee36,
+ 0x65308077,
+ 0xcc8f7a9c,
+ 0xd5afe99c,
+ 0xa3d2f848,
+ 0xbe343aed,
+ 0xc9e5d1d9,
+ 0x7689df57,
+ 0x436efdb9,
+ 0x02fe9c78,
+ 0xbf44d386,
+ 0xd1a7f051,
+ 0x688f8e40,
+ 0xbfc35d3f,
+ 0x8e9ccf1d,
+ 0x265725ce,
+ 0x7b541f84,
+ 0x04b7534a,
+ 0x537689b7,
+ 0xf0196afd,
+ 0xa1c53118,
+ 0xdd4b8f2f,
+ 0x27a4542d,
+ 0x148fc97f,
+ 0xcbb1fe8e,
+ 0xb0f0e359,
+ 0x619182d1,
+ 0x7fe52e97,
+ 0x02112644,
+ 0xde85b69d,
+ 0x6ae60743,
+ 0xc3957d75,
+ 0x55ec9f1c,
+ 0xdf5569a7,
+ 0xff211f65,
+ 0x9f191bb7,
+ 0x27b4ed8e,
+ 0x3d6b7584,
+ 0x1eb61acd,
+ 0x5ab3edfe,
+ 0xb7746746,
+ 0xe202812e,
+ 0xc3a6dad6,
+ 0x6eadbc54,
+ 0xaaf3dbe5,
+ 0x0d5d1241,
+ 0x573db0ba,
+ 0x6acb9a75,
+ 0x355f4aad,
+ 0xb7af5481,
+ 0xd6895cc1,
+ 0x9a3576ae,
+ 0x0a4ce960,
+ 0xea88e6c0,
+ 0xf9777f8c,
+ 0xf5586085,
+ 0x96aa74a0,
+ 0x6ba5f631,
+ 0x98e69a66,
+ 0xa27317f5,
+ 0x7a62af6e,
+ 0x7c640f8c,
+ 0x40bdba17,
+ 0xc3e35f92,
+ 0x257c9a1c,
+ 0x6ae2ba67,
+ 0xd53319a8,
+ 0x82ae2cff,
+ 0x2b2e2602,
+ 0x325499f0,
+ 0x56415add,
+ 0x2f76d62a,
+ 0x13a4fea9,
+ 0x82292dfc,
+ 0x3452de2e,
+ 0x21bc5307,
+ 0xe8dc18ad,
+ 0xa1cfbcfc,
+ 0xa61f387b,
+ 0xfd781889,
+ 0x98e6417a,
+ 0x12df4516,
+ 0xb4946c67,
+ 0x0cecea65,
+ 0x04f28274,
+ 0x9df23422,
+ 0xb4dc8368,
+ 0x8e2010e2,
+ 0x4c304228,
+ 0x99918a5a,
+ 0x44cb62e4,
+ 0xe5d3f6f9,
+ 0xd45ab4f1,
+ 0x15956307,
+ 0x9243a7d6,
+ 0x0c3ee4ca,
+ 0xbfbc5d1b,
+ 0x880c3c65,
+ 0xe9a1e5f7,
+ 0x6573caae,
+ 0x2d971582,
+ 0x2931af83,
+ 0xfbab4eef,
+ 0x9b954125,
+ 0x16e305b1,
+ 0xa2aad029,
+ 0x0c4c4162,
+ 0x2d29f41e,
+ 0xd045716c,
+ 0x836fd651,
+ 0xb8aa8f3a,
+ 0x6f884795,
+ 0x98199e25,
+ 0xecc70aec,
+ 0xf85e31c4,
+ 0x0f06b850,
+/* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
new file mode 100644
index 0000000000..07732198ab
--- /dev/null
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -0,0 +1,293 @@
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "LNXI ";
+ static const char productid[12] = "SE7520JR20 ";
+ struct mp_config_table *mc;
+ unsigned char bus_num;
+ unsigned char bus_isa;
+ unsigned char bus_pxhd_1;
+ unsigned char bus_pxhd_2;
+ unsigned char bus_pxhd_3 = 0;
+ unsigned char bus_pxhd_4 = 0;
+ unsigned char bus_pxhd_x;
+ unsigned char bus_ich5r_1;
+ unsigned int bus_pxhd_id;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ {
+ device_t dev;
+
+ /* ich5r */
+ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
+ if (dev) {
+ bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 0:1f.0, using defaults\n");
+
+ bus_ich5r_1 = 4;
+ bus_isa = 5;
+ }
+ /* pxhd-1 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
+ if (dev) {
+ bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:00.1, using defaults\n");
+
+ bus_pxhd_1 = 2;
+ }
+ /* pxhd-2 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
+ if (dev) {
+ bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+
+ bus_pxhd_2 = 3;
+ }
+ /* test for active riser with 2nd pxh device */
+ dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
+ if (dev) {
+ bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if(bus_pxhd_id == 0x35998086) {
+ bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ /* pxhd-3 */
+ dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
+ if (dev) {
+ bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if(bus_pxhd_id == 0x03298086) {
+ bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ }
+ /* pxhd-4 */
+ dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
+ if (dev) {
+ bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if(bus_pxhd_id == 0x032a8086) {
+ bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ }
+ }
+ }
+ }
+
+ /* define bus and isa numbers */
+ for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* IOAPIC handling */
+
+ smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
+ {
+ struct resource *res;
+ device_t dev;
+ /* pxhd apic 3 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x09, 0x20, res->base);
+ }
+ }
+ else {
+ printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
+ }
+ /* pxhd apic 4 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x0a, 0x20, res->base);
+ }
+ }
+ else {
+ printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
+ }
+ /* pxhd apic 5 */
+ if(bus_pxhd_3) { /* Active riser pxhd */
+ dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x0b, 0x20, res->base);
+ }
+ }
+ else {
+ printk_debug("ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
+ }
+ }
+ /* pxhd apic 6 */
+ if(bus_pxhd_4) { /* active riser pxhd */
+ dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x0c, 0x20, res->base);
+ }
+ }
+ else {
+ printk_debug("ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
+ }
+ }
+ }
+
+
+ /* ISA backward compatibility interrupts */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x08, 0x00);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x01, 0x08, 0x01);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x08, 0x02);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x03, 0x08, 0x03);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x04, 0x08, 0x04);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x06, 0x08, 0x06);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
+ bus_isa, 0x08, 0x08, 0x08);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x09, 0x08, 0x09);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0c, 0x08, 0x0c);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0d, 0x08, 0x0d);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0e, 0x08, 0x0e);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0f, 0x08, 0x0f);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x0a, 0x08, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x0b, 0x08, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x0a, 0x08, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x07, 0x08, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x0b, 0x08, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x05, 0x08, 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x0b, 0x08, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x07, 0x08, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x0b, 0x08, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
+ bus_isa, 0x0a, 0x08, 0x10);
+
+ /* Standard local interrupt assignments */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x00);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x01);
+
+
+#warning "FIXME verify I have the irqs handled for all of the risers"
+ /* 2:3.0 PCI Slot 1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
+
+
+ /* 3:7.0 PCI Slot 2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
+
+ /* PCI Slot 3 (if active riser) */
+ if(bus_pxhd_3) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
+ }
+
+ /* PCI Slot 4 (if active riser) */
+ if(bus_pxhd_4) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
+ }
+
+ /* Onboard SCSI 0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
+
+ /* Onboard SCSI 1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
+
+ /* Onboard NIC 0 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
+
+ /* Onboard NIC 1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
+
+ /* Onboard VGA */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
+
diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c
new file mode 100644
index 0000000000..e9008a40dc
--- /dev/null
+++ b/src/mainboard/intel/jarrell/power_reset_check.c
@@ -0,0 +1,12 @@
+
+static void power_down_reset_check(void)
+{
+ uint8_t cmos;
+
+ cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
+ print_debug("Boot byte = ");
+ print_debug_hex8(cmos);
+ print_debug("\r\n");
+
+ if((cmos>2)&&(cmos&1)) full_reset();
+}
diff --git a/src/mainboard/intel/jarrell/reset.c b/src/mainboard/intel/jarrell/reset.c
new file mode 100644
index 0000000000..874bfc4848
--- /dev/null
+++ b/src/mainboard/intel/jarrell/reset.c
@@ -0,0 +1,40 @@
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#ifndef __ROMCC__
+#include <device/device.h>
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+#define PCI_DEV_INVALID 0
+
+static inline device_t pci_locate_device(unsigned pci_id, device_t from)
+{
+ return dev_find_device(pci_id >> 16, pci_id & 0xffff, from);
+}
+#endif
+
+void soft_reset(void)
+{
+ outb(0x04, 0xcf9);
+}
+void hard_reset(void)
+{
+ outb(0x02, 0xcf9);
+ outb(0x06, 0xcf9);
+}
+void full_reset(void)
+{
+ device_t dev;
+ /* Enable power on after power fail... */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801ER_ISA), 0);
+ if (dev != PCI_DEV_INVALID) {
+ unsigned byte;
+ byte = pci_read_config8(dev, 0xa4);
+ byte &= 0xfe;
+ pci_write_config8(dev, 0xa4, byte);
+
+ }
+ outb(0x0e, 0xcf9);
+}
+
+
diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c
new file mode 100644
index 0000000000..29e8ba36f6
--- /dev/null
+++ b/src/mainboard/intel/jarrell/watchdog.c
@@ -0,0 +1,138 @@
+#include <device/pnp_def.h>
+
+#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
+#define NSC_WDBASE 0x600
+#define ICH5_WDBASE 0x400
+#define ICH5_GPIOBASE 0x500
+
+static void disable_sio_watchdog(device_t dev)
+{
+ /* FIXME move me somewhere more appropriate */
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 1);
+ pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
+ /* disable the sio watchdog */
+ outb(0, NSC_WDBASE + 0);
+ pnp_set_enable(dev, 0);
+}
+
+static void disable_ich5_watchdog(void)
+{
+ /* FIXME move me somewhere more appropriate */
+ device_t dev;
+ unsigned long value, base;
+ dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
+ if (dev == PCI_DEV_INVALID) {
+ die("Missing ich5?");
+ }
+ /* Enable I/O space */
+ value = pci_read_config16(dev, 0x04);
+ value |= (1 << 10);
+ pci_write_config16(dev, 0x04, value);
+
+ /* Set and enable acpibase */
+ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
+ pci_write_config8(dev, 0x44, 0x10);
+ base = ICH5_WDBASE + 0x60;
+
+ /* Set bit 11 in TCO1_CNT */
+ value = inw(base + 0x08);
+ value |= 1 << 11;
+ outw(value, base + 0x08);
+
+ /* Clear TCO timeout status */
+ outw(0x0008, base + 0x04);
+ outw(0x0002, base + 0x06);
+}
+
+static void disable_jarell_frb3(void)
+{
+ device_t dev;
+ unsigned long value, base;
+ dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
+ if (dev == PCI_DEV_INVALID) {
+ die("Missing ich5?");
+ }
+ /* Enable I/O space */
+ value = pci_read_config16(dev, 0x04);
+ value |= (1 << 0);
+ pci_write_config16(dev, 0x04, value);
+
+ /* Set gpio base */
+ pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
+ base = ICH5_GPIOBASE;
+
+ /* Enable GPIO Bar */
+ value = pci_read_config32(dev, 0x5c);
+ value |= 0x10;
+ pci_write_config32(dev, 0x5c, value);
+
+ /* Configure GPIO 48 and 40 as GPIO */
+ value = inl(base + 0x30);
+ value |= (1 << 16) | ( 1 << 8);
+ outl(value, base + 0x30);
+
+ /* Configure GPIO 48 as Output */
+ value = inl(base + 0x34);
+ value &= ~(1 << 16);
+ outl(value, base + 0x34);
+
+ /* Toggle GPIO 48 high to low */
+ value = inl(base + 0x38);
+ value |= (1 << 16);
+ outl(value, base + 0x38);
+ value &= ~(1 << 16);
+ outl(value, base + 0x38);
+
+}
+
+static void disable_watchdogs(void)
+{
+ disable_sio_watchdog(NSC_WD_DEV);
+ disable_ich5_watchdog();
+ disable_jarell_frb3();
+ print_debug("Watchdogs disabled\r\n");
+}
+
+static void ich5_watchdog_on(void)
+{
+ device_t dev;
+ unsigned long value, base;
+ unsigned char byte;
+
+ /* check cmos options */
+ byte = cmos_read(RTC_BOOT_BYTE-1);
+ if(!(byte & 1)) return; /* no boot watchdog */
+ byte = cmos_read(RTC_BOOT_BYTE);
+ if(!(byte & 2)) return; /* fallback so ignore */
+
+ dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
+ if (dev == PCI_DEV_INVALID) {
+ die("Missing ich5?");
+ }
+ /* Enable I/O space */
+ value = pci_read_config16(dev, 0x04);
+ value |= (1 << 10);
+ pci_write_config16(dev, 0x04, value);
+
+ /* Set and enable acpibase */
+ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
+ pci_write_config8(dev, 0x44, 0x10);
+ base = ICH5_WDBASE + 0x60;
+
+ /* Clear TCO timeout status */
+ outw(0x0008, base + 0x04);
+ outw(0x0002, base + 0x06);
+
+ /* set the time value 1 cnt = .6 sec */
+ outw(0x0010, base + 0x01);
+ /* reload the timer with the value */
+ outw(0x0001, base + 0x00);
+
+ /* clear bit 11 in TCO1_CNT to start watchdog */
+ value = inw(base + 0x08);
+ value &= ~(1 << 11);
+ outw(value, base + 0x08);
+
+ print_debug("Watchdog ICH5 enabled\r\n");
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 05:06:10 +0000