diff options
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/bayleybay_fsp/romstage.c | 26 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/spd/spd_util.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/cougar_canyon2/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/spd/spd_util.c | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/strago/gpio.c | 10 |
5 files changed, 22 insertions, 22 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index d98802344c..199a15e3e6 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -65,67 +65,67 @@ const uint32_t mAzaliaVerbTableData13[] = { /* *ALC262 Verb Table - 10EC0262 */ - /* Pin Complex (NID 0x11 ) */ + /* Pin Complex (NID 0x11) */ 0x01171CF0, 0x01171D11, 0x01171E11, 0x01171F41, - /* Pin Complex (NID 0x12 ) */ + /* Pin Complex (NID 0x12) */ 0x01271CF0, 0x01271D11, 0x01271E11, 0x01271F41, - /* Pin Complex (NID 0x14 ) */ + /* Pin Complex (NID 0x14) */ 0x01471C10, 0x01471D40, 0x01471E01, 0x01471F01, - /* Pin Complex (NID 0x15 ) */ + /* Pin Complex (NID 0x15) */ 0x01571CF0, 0x01571D11, 0x01571E11, 0x01571F41, - /* Pin Complex (NID 0x16 ) */ + /* Pin Complex (NID 0x16) */ 0x01671CF0, 0x01671D11, 0x01671E11, 0x01671F41, - /* Pin Complex (NID 0x18 ) */ + /* Pin Complex (NID 0x18) */ 0x01871C20, 0x01871D98, 0x01871EA1, 0x01871F01, - /* Pin Complex (NID 0x19 ) */ + /* Pin Complex (NID 0x19) */ 0x01971C21, 0x01971D98, 0x01971EA1, 0x01971F02, - /* Pin Complex (NID 0x1A ) */ + /* Pin Complex (NID 0x1A) */ 0x01A71C2F, 0x01A71D30, 0x01A71E81, 0x01A71F01, - /* Pin Complex (NID 0x1B ) */ + /* Pin Complex (NID 0x1B) */ 0x01B71C1F, 0x01B71D40, 0x01B71E21, 0x01B71F02, - /* Pin Complex (NID 0x1C ) */ + /* Pin Complex (NID 0x1C) */ 0x01C71CF0, 0x01C71D11, 0x01C71E11, 0x01C71F41, - /* Pin Complex (NID 0x1D ) */ + /* Pin Complex (NID 0x1D) */ 0x01D71C01, 0x01D71DC6, 0x01D71E14, 0x01D71F40, - /* Pin Complex (NID 0x1E ) */ + /* Pin Complex (NID 0x1E) */ 0x01E71CF0, 0x01E71D11, 0x01E71E11, 0x01E71F41, - /* Pin Complex (NID 0x1F ) */ + /* Pin Complex (NID 0x1F) */ 0x01F71CF0, 0x01F71D11, 0x01F71E11, diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 4e2f31fc4b..31f5452603 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -23,7 +23,7 @@ void mainboard_fill_dq_map_ch0(void *dq_map_ptr) { /* DQ byte map Ch0 */ const u8 dq_map[12] = { - 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 , + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 38af2b881b..f6c867a001 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -261,7 +261,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { /* For reference print FSP version */ u32 version = MCHBAR32(0x5034); printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n", - version >> 24 , (version >> 16) & 0xff, + version >> 24, (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 676f84d01c..fc0581cb24 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -26,9 +26,9 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr) { /* DQ byte map */ const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index fa24594ee0..ed9ae4b4d1 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -69,7 +69,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ @@ -131,11 +131,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPIO_NC, /* 76 GPI SATA_GP1 */ - GPIO_INPUT_PU_20K, /* 77 SATA_LEDN , EC_IN_RW */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */ GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ Native_M1, /* 90 PCIE_CLKREQ0B */ @@ -162,7 +162,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPIO_NC, /* 06 GPIO_DFX8 */ GPIO_NC, /* 07 GPIO_DFX2 */ GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data, UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), |