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-rw-r--r--src/mainboard/intel/tglrvp/romstage_fsp_params.c9
-rw-r--r--src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c76
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c76
4 files changed, 83 insertions, 80 deletions
diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
index 47507f4eed..33415684ed 100644
--- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
@@ -42,14 +42,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
- const struct lpddr4x_cfg *mem_config = variant_memory_params();
- const struct spd_info spd_info = {
- .topology = MEMORY_DOWN,
- .md_spd_loc = SPD_CBFS,
+ const struct mb_cfg *mem_config = variant_memory_params();
+ const struct mem_spd spd_info = {
+ .topo = MEM_TOPO_MEMORY_DOWN,
.cbfs_index = mainboard_get_spd_index(),
};
bool half_populated = false;
- meminit_lpddr4x(mem_cfg, mem_config, &spd_info, half_populated);
+ memcfg_init(mem_cfg, mem_config, &spd_info, half_populated);
}
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
index bad9e9e828..fbb86f7b00 100644
--- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
@@ -15,6 +15,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
size_t variant_memory_sku(void);
-const struct lpddr4x_cfg *variant_memory_params(void);
+const struct mb_cfg *variant_memory_params(void);
#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
index 490a14591c..e965e6bfc9 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
@@ -9,59 +9,61 @@ size_t __weak variant_memory_sku(void)
return 0;
}
-static const struct lpddr4x_cfg mem_config = {
+static const struct mb_cfg mem_config = {
+ .type = MEM_TYPE_LP4X,
+
/* DQ byte map */
- .dq_map = {
- [0] = {
- { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */
- { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */
+ .lp4x_dq_map = {
+ .ddr0 = {
+ .dq0 = { 0, 1, 6, 7, 3, 2, 5, 4, }, /* DDR0_DQ0[7:0] */
+ .dq1 = { 15, 8, 9, 14, 12, 11, 10, 13, }, /* DDR1_DQ1[7:0] */
},
- [1] = {
- { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */
- { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */
+ .ddr1 = {
+ .dq0 = { 11, 12, 8, 15, 9, 14, 10, 13, }, /* DDR1_DQ0[7:0] */
+ .dq1 = { 3, 4, 7, 0, 6, 1, 5, 2, }, /* DDR1_DQ1[7:0] */
},
- [2] = {
- { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */
- { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */
+ .ddr2 = {
+ .dq0 = { 4, 5, 3, 2, 7, 1, 0, 6, }, /* DDR2_DQ0[7:0] */
+ .dq1 = { 11, 10, 12, 13, 8, 9, 14, 15, }, /* DDR2_DQ1[7:0] */
},
- [3] = {
- { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */
- { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */
+ .ddr3 = {
+ .dq0 = { 12, 11, 8, 13, 14, 15, 9, 10, }, /* DDR3_DQ0[7:0] */
+ .dq1 = { 4, 7, 3, 2, 1, 6, 0, 5, }, /* DDR3_DQ1[7:0] */
},
- [4] = {
- { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */
- { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */
+ .ddr4 = {
+ .dq0 = { 11, 10, 9, 8, 12, 13, 15, 14, }, /* DDR4_DQ0[7:0] */
+ .dq1 = { 4, 5, 6, 7, 3, 2, 0, 1, }, /* DDR4_DQ1[7:0] */
},
- [5] = {
- { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */
- { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */
+ .ddr5 = {
+ .dq0 = { 0, 7, 1, 6, 3, 5, 2, 4, }, /* DDR5_DQ0[7:0] */
+ .dq1 = { 9, 8, 10, 11, 14, 15, 13, 12, }, /* DDR5_DQ1[7:0] */
},
- [6] = {
- { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */
- { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */
+ .ddr6 = {
+ .dq0 = { 4, 5, 6, 1, 3, 2, 7, 0, }, /* DDR6_DQ0[7:0] */
+ .dq1 = { 10, 13, 12, 11, 14, 9, 15, 8, }, /* DDR6_DQ1[7:0] */
},
- [7] = {
- { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */
- { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */
+ .ddr7 = {
+ .dq0 = { 10, 12, 9, 15, 8, 11, 13, 14, }, /* DDR7_DQ0[7:0] */
+ .dq1 = { 3, 4, 1, 2, 6, 0, 5, 7, }, /* DDR7_DQ1[7:0] */
},
},
/* DQS CPU<>DRAM map */
- .dqs_map = {
- [0] = { 0, 1 }, /* DDR0_DQS[1:0] */
- [1] = { 1, 0 }, /* DDR1_DQS[1:0] */
- [2] = { 0, 1 }, /* DDR2_DQS[1:0] */
- [3] = { 1, 0 }, /* DDR3_DQS[1:0] */
- [4] = { 1, 0 }, /* DDR4_DQS[1:0] */
- [5] = { 0, 1 }, /* DDR5_DQS[1:0] */
- [6] = { 0, 1 }, /* DDR6_DQS[1:0] */
- [7] = { 1, 0 }, /* DDR7_DQS[1:0] */
+ .lp4x_dqs_map = {
+ .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */
+ .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */
+ .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */
+ .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */
+ .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */
+ .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */
+ .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */
},
- .ect = 1, /* Early Command Training */
+ .ect = true, /* Early Command Training */
};
-const struct lpddr4x_cfg *__weak variant_memory_params(void)
+const struct mb_cfg *__weak variant_memory_params(void)
{
return &mem_config;
}
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
index ca60357e84..8e7bb14ba0 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
@@ -9,59 +9,61 @@ size_t __weak variant_memory_sku(void)
return 0;
}
-static const struct lpddr4x_cfg mem_config = {
+static const struct mb_cfg mem_config = {
+ .type = MEM_TYPE_LP4X,
+
/* DQ byte map */
- .dq_map = {
- [0] = {
- { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */
- { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */
+ .lp4x_dq_map = {
+ .ddr0 = {
+ .dq0 = { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */
+ .dq1 = { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */
},
- [1] = {
- { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */
- { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */
+ .ddr1 = {
+ .dq0 = { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */
+ .dq1 = { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */
},
- [2] = {
- { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */
- { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */
+ .ddr2 = {
+ .dq0 = { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */
+ .dq1 = { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */
},
- [3] = {
- { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */
- { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */
+ .ddr3 = {
+ .dq0 = { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */
+ .dq1 = { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */
},
- [4] = {
- { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */
- { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */
+ .ddr4 = {
+ .dq0 = { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */
+ .dq1 = { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */
},
- [5] = {
- { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */
- { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */
+ .ddr5 = {
+ .dq0 = { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */
+ .dq1 = { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */
},
- [6] = {
- { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */
- { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */
+ .ddr6 = {
+ .dq0 = { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */
+ .dq1 = { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */
},
- [7] = {
- { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */
- { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */
+ .ddr7 = {
+ .dq0 = { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */
+ .dq1 = { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */
},
},
/* DQS CPU<>DRAM map */
- .dqs_map = {
- [0] = { 1, 0 }, /* DDR0_DQS[1:0] */
- [1] = { 0, 1 }, /* DDR1_DQS[1:0] */
- [2] = { 0, 1 }, /* DDR2_DQS[1:0] */
- [3] = { 1, 0 }, /* DDR3_DQS[1:0] */
- [4] = { 1, 0 }, /* DDR4_DQS[1:0] */
- [5] = { 0, 1 }, /* DDR5_DQS[1:0] */
- [6] = { 0, 1 }, /* DDR6_DQS[1:0] */
- [7] = { 1, 0 }, /* DDR7_DQS[1:0] */
+ .lp4x_dqs_map = {
+ .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR0_DQS[1:0] */
+ .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */
+ .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */
+ .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR4_DQS[1:0] */
+ .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */
+ .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */
+ .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */
},
- .ect = 1, /* Early Command Training */
+ .ect = true, /* Early Command Training */
};
-const struct lpddr4x_cfg *__weak variant_memory_params(void)
+const struct mb_cfg *__weak variant_memory_params(void)
{
return &mem_config;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 22:08:32 +0000